LX128EV-5FN208C Lattice, LX128EV-5FN208C Datasheet - Page 36

• Manufacturer Part Number: LX128EV-5FN208C
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 3.3V, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128EV-5FN208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters
Lattice Semiconductor
Input/Output Delays
t
t
t
t
t
t
t
t
t
t
Shift Register and MUX Delays
t
t
t
t
AND Arrays and Routing Delays
t
t
t
t
t
t
t
t
t
t
t
t
Register/Latch Delays, Output Paths
t
t
t
t
t
t
t
t
BUF
CLK_IN
CLKEN_IN
DIS
EN
GOE_IN
IN
SEL_IN
SR_IN
TOE_IN
IPAC
OPAC
MUXPD
MUXSEL
FIFODATAOUT
GCLK
HSIFIFOFLAG
HSIOUT
HSISSCLKOUT
PLL_DELAY
PTCLK
PTCLKEN
PTOE
PTSEL
PTSR
ROUTEGRP
OPASROi
OPASRRi
OPBYPASS
OPCEHi
OPCESi
OPCESi_PT
OPCOi
OPHi
Parameter
Output Buffer Delay
Global Clock Input Delay
Global Clock Enable Input Delay
Output Disable Delay
Output Enable Delay
Global Output Enable Path Delay
Input Pin Delay
Global MUX Select Input Delay
Global Set/Reset Path Delay
Test Output Enable Path Delay
Input Path Adjacent I/O Cell Delay
(Shift Register)
Output Path Adjacent I/O Cell Delay
(Shift Register)
MUX Data Path Delay
MUX Select Path Delay
FIFO Output to I/O Block Delay
Clock Tree Delay
HSI/FIFO Flag to I/O Block Delay
HSI Output to I/O Cell Block Delay
HSI Source Synchronous Clock to I/O Cell
Block Delay
PLL Delay Increment
Clock AND Array Delay
Clock Enable AND Array Delay
OE AND Array Delay
Select AND Array Delay
Set/Reset AND Array Delay
Global Routing Pool Delay
Asynchronous Set/Reset to Output
Asynchronous Set/Reset Recovery
Register/Latch Bypass Delay
Register Clock Enable Hold Time
Register Clock Enable Setup Time
(Global Clock Enable)
Register Clock Enable Setup Time
(Product Term Clock Enable)
Register Clock to Output Delay
Register Hold Time
Description
Over Recommended Operating Conditions
33
Min.
1.30
1.10
1.00
0.80
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-3
Max.
0.80
1.00
1.80
1.80
1.50
2.00
0.40
1.60
2.00
3.70
0.80
1.30
0.90
0.40
0.00
0.40
0.00
0.00
0.00
0.33
2.20
2.10
2.40
1.70
1.40
0.90
2.50
2.50
0.00
0.70
—
—
—
—
Min.
1.30
1.10
1.00
0.80
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-32
Max.
0.80
1.00
1.80
1.80
1.80
2.00
0.40
1.60
2.70
3.70
0.80
1.30
0.90
0.40
0.00
0.40
0.00
0.00
0.00
0.33
2.20
2.10
2.40
1.70
1.40
0.90
2.50
2.50
0.20
0.90
—
—
—
—
ispGDX2 Family Data Sheet
Min.
1.30
1.10
2.10
0.80
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-35
Max.
0.80
1.00
1.80
2.50
2.50
2.00
0.40
1.60
2.70
3.70
0.80
1.30
0.90
0.40
0.00
0.40
0.00
0.00
0.00
0.33
2.20
2.10
2.40
1.70
2.70
0.90
2.50
2.50
0.50
1.00
—
—
—
—
1
Min.
2.17
1.83
3.50
1.33
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-5
Max.
1.14
1.67
3.00
4.17
4.17
3.33
0.57
2.29
4.50
6.17
1.33
2.17
1.29
0.57
0.00
0.67
0.00
0.00
0.00
0.33
3.67
3.50
4.00
2.83
4.50
1.29
4.17
4.17
0.71
1.67
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns