LX64V-5F100C Lattice, LX64V-5F100C Datasheet - Page 38
LX64V-5F100C
Manufacturer Part Number
LX64V-5F100C
Description
Analog & Digital Crosspoint ICs 3.3V 64 I/O
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX64V-5F100C
Maximum Dual Supply Voltage
3.6 V
Minimum Dual Supply Voltage
3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
3.3 V
Supply Type
Triple
Configuration
64 x 64
Package / Case
FPBGA-100
Data Rate
11 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LX64V-5F100C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
ispGDX2V/B/C, ispGDX2EV/EB/EC Internal Timing Parameters
Lattice Semiconductor
t
t
t
t
t
1. Internal parameters are not tested and are for reference only. Refer to the timing model in this data sheet for details.
2. t
OELSi
OELSi_PT
OESi
OESi_PT
OESRPWi
Parameter
given in the sysCLOCK PLL Timing section) in either direction in steps of size t
PLL_DELAY
is the unit of increment by which the clock signal can be incremented. The PLL can adjust the clock signal by up to t
Latch Setup Time (Global Gate)
Latch Setup Time (Product Term Gate)
Register Setup Time (Global Clock)
Register Setup Time (Product Term Clock)
Asynchronous Set/Reset Pulse Width
Description
Over Recommended Operating Conditions
35
Min.
1.40
1.00
1.00
1.00
—
-3
Max.
2.50
—
—
—
—
PLL_DELAY.
Min.
1.40
1.00
1.00
1.00
—
-32
Max.
2.50
—
—
—
—
ispGDX2 Family Data Sheet
Min.
1.40
1.00
1.40
1.00
—
-35
Max.
2.50
—
—
—
—
1
(Continued)
Min.
2.33
1.67
2.33
1.67
—
-5
Max.
4.17
—
—
—
—
RANGE
Timing v.2.2
Units
(as
ns
ns
ns
ns
ns