LX128V-32F208C Lattice, LX128V-32F208C Datasheet - Page 4

• Manufacturer Part Number: LX128V-32F208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 3.3V, SERDES, 3.2ns
• Manufacturer: Lattice

Specifications of LX128V-32F208C

• Maximum Dual Supply Voltage: 3.6 V
• Minimum Dual Supply Voltage: 3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 3.3 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

September 2005
Features
■ High Performance Bus Switching
■ sysCLOCK™ PLL
■ sysIO™ Interfacing
Table 1. ispGDX2 Family Selection Guide
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I/Os
GDX Blocks
t
t
t
f
Max Bandwidth
sysHSI Channels
LVDS/Bus LVDS (Pairs)
PLLs
Package
1. Max number of SERDES channels per device * 800Mbps
2. “E-Series” does not support sysHSI.
3. f
PD
S
CO
MAX
MAX
(Toggle)
• High bandwidth
• Up to 16 (15x10) FIFOs for data buffering
• High speed performance
• Built-in programmable control logic capability
• I/O intensive: 64 to 256 I/Os
• Expanded MUX capability up to 188:1 MUX
• Frequency synthesis and skew management
• Clock multiply and divide capability
• Clock shifting up to +/-2.35ns in 335ps steps
• Up to four PLLs
• LVCMOS 1.8, 2.5, 3.3 and LVTTL support for
• SSTL 2/3 Class I and II support
• HSTL Class I, III and IV support
• GTL+, PCI-X for bus interfaces
• LVPECL, LVDS and Bus LVDS differential support
• Hot socketing
• Programmable drive strength
(Toggle) * maximum I/Os divided by 2.
standard board interfaces
– Up to 12.8 Gbps (SERDES)
– Up to 38 Gbps (without SERDES)
– f
– t
– t
– t
MAX
PD
CO
S
= 2.0ns
= 3.0ns
= 2.9ns
2
= 360MHz
SERDES
Without SERDES
1, 2
3
100-ball fpBGA
ispGDX2-64/E
360MHz
3.2Gbps
11Gbps
3.0ns
2.0ns
2.9ns
64
32
4
4
2
1
■ Two Options Available
■ sysHSI Blocks Provide up to 16 High-speed
■ Flexible Programming and Testing
High Performance Interfacing and Switching
Channels
• High-performance sysHSI (standard part number)
• Low-cost, no sysHSI (“E-Series”)
• Serializer/de-serializer (SERDES) included
• Clock Data Recovery (CDR) built in
• 800 Mbps per channel
• LVDS differential support
• 10B/12B support
• 8B/10B support
• Source Synchronous support
• IEEE 1532 compliant In-System Programmabil-
• Boundary scan test through IEEE 1149.1
• 3.3V, 2.5V or 1.8V power supplies
• 5V tolerant I/O for LVCMOS 3.3 and LVTTL
ity (ISP™)
interface
interfaces
– Encoding / decoding
– Bit alignment
– Symbol alignment
– Bit alignment
– Symbol alignment
ispGDX2-128/E
208-ball fpBGA
ispGDX2 Family
330MHz
6.4Gbps
21Gbps
3.2ns
2.0ns
3.1ns
128
64
8
8
2
™
ispGDX2-256/E
484-ball fpBGA
12.8Gbps
300MHz
38Gbps
3.5ns
2.0ns
3.2ns
256
128
16
16
4
gdx2fam_13
Data Sheet