DS26528G Maxim Integrated Products, DS26528G Datasheet - Page 126
![no-image](/images/manufacturer_photos/0/4/417/maxim_integrated_products_sml.jpg)
DS26528G
Manufacturer Part Number
DS26528G
Description
Network Controller & Processor ICs Octal E1-T1-J1 Singl e-Chip Transceiver (
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528G
Product
Framer
Number Of Transceivers
8
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
875 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TE-CSBGA
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AFATECH
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Part Number:
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- Current page: 126 of 276
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bits 4 to 0: Receive Channel Monitor Bits (RCM[4:0]). RCM0 is the LSB of a 5-bit channel select that
determines which receive DS0 channel data will appear in the RDS0M register.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit 4 (T1 Mode): Receive Force Signaling All Ones (RFSA1).
Bit 4 (E1 Mode): CAS Mode Select (CASMS).
Bit 2: Receive-Signaling Force Freeze (RSFF). Freezes receive-side signaling at RSIG (and RSER if receive-
signaling reinsertion is enabled); will override receive freeze enable (RFE).
Bit 1: Receive-Signaling Freeze Enable (RSFE).
Bit 0: Receive-Signaling Integration Enable (RSIE).
0 = do not force robbed bit signaling to all ones
1 = force signaling bits to all ones on a per-channel basis according to the
0 = The DS26528 will initiate a resync when two consecutive multiframe alignment signals have been
received with an error.
1 = The DS26528 will initiate a resync when two consecutive multiframe alignment signals have been
received with an error, or 1 multiframe has been received with all the bits in time slot 16 in state 0.
Alignment criteria is met when at least one bit in state 1 is present in the time slot 16 preceding the
multiframe alignment signal first detected (G.732 alternate criteria).
0 = do not force a freeze event
1 = force a freeze event
0 = no freezing of receive-signaling data will occur
1 = allow freezing of receive-signaling data at RSIG (and RSER if receive-signaling reinsertion is enabled)
0 = signaling changes of state reported on any change in selected channels
1 = signaling must be stable for three multiframes in order for a change of state to be reported
—
—
—
7
0
7
0
RDS0SEL
Receive Channel Monitor Select Register
012h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RSIGC
Receive-Signaling Control Register
013h + (200h x n): where n = 0 to 7, for Ports 1 to 8
—
—
—
6
0
6
0
—
—
—
5
0
5
0
CASMS
RFSA1
126 of 276
RCM4
4
0
4
0
RCM3
—
—
3
0
3
0
DS26528 Octal T1/E1/J1 Transceiver
RCM2
RSFF
RSFF
2
0
2
0
T1RSAOI1:T1RSAOI3
RCM1
RSFE
RSFE
1
0
1
0
RCM0
registers.
RSIE
RSIE
0
0
0
0
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