DS26528G Maxim Integrated Products, DS26528G Datasheet - Page 161
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DS26528G
Manufacturer Part Number
DS26528G
Description
Network Controller & Processor ICs Octal E1-T1-J1 Singl e-Chip Transceiver (
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528G
Product
Framer
Number Of Transceivers
8
Supply Voltage (max)
3.465 V
Supply Voltage (min)
3.135 V
Supply Current (max)
875 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Package / Case
TE-CSBGA
Available stocks
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Manufacturer
Quantity
Price
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AFATECH
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: All bits in this register are latched and can create interrupts.
Bit 7: Receive Elastic Store Full Event (RESF). Set when the receive elastic store buffer fills and a frame is
deleted.
Bit 6: Receive Elastic Store Empty Event (RESEM). Set when the receive elastic store buffer empties and a
frame is repeated.
Bit 5: Receive Elastic Store Slip Occurrence Event (RSLIP). Set when the receive elastic store has either
repeated or deleted a frame.
Bit 3: Receive-Signaling Change-of-State Event (RSCOS). Set when any channel selected by the Receive-
Signaling Change-of-State Interrupt Enable registers (RSCSE1:RSCSE3) changes signaling state.
Bit 2: One-Second Timer (1SEC). Set on every one-second interval based on RCLK.
Bit 1: Timer Event (TIMER). This status bit indicates that the performance monitor counters have been updated
and are available to be read by the host. The error counter update interval as determined by the settings in the
Error Counter Configuration register (ERCNT).
Bit 0: Receive Multiframe Event (RMF).
T1 Mode: Set on increments of one second or 42ms based on RCLK, or a manual latch event.
E1 Mode: Set on increments of one second or 62.5ms based on RCLK, or a manual latch event.
T1 Mode: Set every 1.5ms on D4 MF boundaries or every 3ms on ESF MF boundaries.
E1 Mode: Set every 2.0ms on receive CAS multiframe boundaries to alert host the signaling data is
available. Continues to set on an arbitrary 2.0ms boundary when CAS signaling is not enabled.
RESF
7
0
RLS4
Receive Latched Status Register 4
093h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RESEM
6
0
RSLIP
5
0
161 of 276
—
4
0
RSCOS
3
0
DS26528 Octal T1/E1/J1 Transceiver
1SEC
2
0
TIMER
1
0
RMF
0
0
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