DS33R11 Maxim Integrated Products, DS33R11 Datasheet - Page 2

• Manufacturer Part Number: DS33R11
• Description: Network Controller & Processor ICs Ethernet Mapper with Integrated T1-E1-J1
• Manufacturer: Maxim Integrated Products

Specifications of DS33R11

• Product: Framer
• Number Of Transceivers: 1
• Supply Voltage (max): 1.89 V, 3.465 V
• Supply Voltage (min): 1.71 V, 3.135 V
• Supply Current (max): 100 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Package / Case: BGA

1
2
3
4
5
6
7
8
9
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10 C
2.11 J
2.12 T1/E1/J1 F
2.13 TDM B
2.14 T
2.15 S
7.1
8.1
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10 S
9.11 C
9.12 A
9.13 F
9.14 E
DESCRIPTION ................................................................................................................................... 9
FEATURE HIGHLIGHTS.................................................................................................................. 11
APPLICATIONS ............................................................................................................................... 17
ACRONYMS AND GLOSSARY ....................................................................................................... 18
MAJOR OPERATING MODES ........................................................................................................ 19
BLOCK DIAGRAMS......................................................................................................................... 20
PIN DESCRIPTIONS ........................................................................................................................ 25
FUNCTIONAL DESCRIPTION ......................................................................................................... 41
8.1.1
8.1.2
8.1.3
ETHERNET MAPPER ...................................................................................................................... 43
9.1.1
9.1.2
9.13.1 Full Duplex Flow Control.......................................................................................................................54
9.13.2 Half Duplex Flow Control ......................................................................................................................55
9.13.3 Host-Managed Flow Control .................................................................................................................55
G
M
HDLC E
X.86 (L
A
C
SDRAM I
MAC I
T1/E1/J1 L
P
P
E
R
I
G
P
D
I
S
I
NITIALIZATION AND
NTERRUPT
NFORMATION
ITTER
EST AND
LOW
DDITIONAL
PECIFICATIONS
IN
ROCESSOR
THERNET
ER
TATUS
ERIAL
RBITER
THERNET
OMMITTED
LOCK
ESETS AND
EVICE
ONNECTIONS AND
ENERAL
LOBAL
ICROPROCESSOR
F
Read-Write/Data Strobe Modes............................................................................................................42
Clear on Read .......................................................................................................................................42
Interrupt and Pin Modes........................................................................................................................42
Ethernet Interface Clock Modes............................................................................................................45
Serial Interface Clock Modes ................................................................................................................45
-P
UNCTIONAL
C
NTERFACE
ORT
A
US
S
INK
I
I
ONTROL
NTERFACE
R
R
THERNET
NTERRUPTS
TTENUATOR
YNTHESIZER
....................................................................................................................................... 52
...................................................................................................................................... 11
NTERFACE
EGISTERS
ESOURCES
D
..................................................................................................................................... 14
M
R
I
A
INE
RAMER
I
NTERFACE
IAGNOSTICS
HDLC C
NFORMATION
I
CCESS
ESOURCES
I
APPER
L
NFORMATION
NTERFACE
R
OW
I
NTERFACE
EGISTERS
............................................................................................................................ 53
C
........................................................................................................................... 12
D
M
P
OMPLIANCE
ESCRIPTION
........................................................................................................................ 14
........................................................................................................................ 50
C
I
Q
OWER
P
NTERFACE
APPING
...................................................................................................................... 12
C
...................................................................................................................... 50
..................................................................................................................... 13
..................................................................................................................... 48
ONTROLLERS IN THE
ONFIGURATION
.................................................................................................................... 13
.................................................................................................................... 47
UEUES
ROTOCOL FOR
LOCKS
P
................................................................................................................ 15
................................................................................................................ 47
ORT
............................................................................................................... 42
R
............................................................................................................. 50
M
R
............................................................................................................ 13
EGISTERS
.......................................................................................................... 11
ATE
ODES
......................................................................................................... 43
......................................................................................................... 51
......................................................................................................... 56
....................................................................................................... 16
...................................................................................................... 11
...................................................................................................... 25
TABLE OF CONTENTS
(CIR) C
................................................................................................. 46
.............................................................................................. 47
SONET/SDH) E
........................................................................................... 50
ONTROLLER
I
2 of 344
NTEGRATED
.................................................................... 12
THERNET
T1/E1/J1 T
M
APPING
RANSCEIVER
....................................... 11
............................ 12