DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 112

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

10.12 LIU – Line Interface Unit
10.12.1 General Description
The line interface units (LIUs) perform the functions necessary for interfacing at the physical layer to DS3 or E3
lines. The LIU has independent receive and transmit paths and a built-in jitter attenuator. See
location within the DS3170 device of the LIU.
Figure 10-30. LIU Functional Diagram
10.12.2 Features
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10.12.2.1 Transmitter
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10.12.2.2 Receiver
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10.12.3 Detailed Description
The receiver performs clock and data recovery from an alternate mark inversion (AMI) coded signal or a B3ZS- or
HDB3-coded AMI signal and monitors for loss of the incoming signal. The transmitter drives standard pulse-shape
Clock Rate
Performs Receive Clock/Data Recovery and Transmit Waveshaping
Jitter Attenuators can be Placed in Either the Receive or Transmit Paths
Interfaces to 75Ω Coaxial Cable at Lengths Up to 380 meters (DS3), 440 meters (E3)
Use 1:2 Transformers on Tx and RX
Requires Minimal External Components
Local and Remote Loopbacks
Gapped clock capable up to 52MHz
Wide 50 ±20% transmit clock duty cycle
Clock inversion for glueless interfacing
Unframed all-ones generator (E3 AIS)
Line build-out (LBO) control
Tri-state line driver outputs support protection switching applications
Per-channel power-down control
Output driver monitor
AGC/equalizer block handles from 0 to 15dB of cable loss
Loss-of-lock (LOL) PLL status indication
Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp
Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775)
Clock inversion for glueless interfacing
Per-channel power-down control
Receive
Transmit
DS3/E3
DS3/E3
Adapter
LIU
LIU
Encoder
Decoder
B3ZS/
B3ZS/
HDB3
HDB3
TUA1
TAIS
IEEE P1149.1
JTAG Test
Access Port
FEAC
DS3 / E3
Framer
DS3 / E3
Transmit
Receive
Formatter
Buffer
Trace
Trail
HDLC
112 of 230
GEN
UA1
DS3170 DS3/E3 Single-Chip Transceiver
RX BERT
TX BERT
Microprocessor
Interface
Figure 10-30
for the