DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 55

• Manufacturer Part Number: DS3170
• Description: Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
• Manufacturer: Maxim Integrated Products

Figure 10-1. Interrupt Structure
Figure 10-1
enable a particular interrupt. Each block has a Status Register Interrupt Enable register which must be set in order
to enable an interrupt. The next step is to unmask the interrupt at the port level. This is controlled in the Global
Interrupt Status Register Interrupt Enable register (GL.ISRIE). Now the device is ready to drive the INT pin low
when a particular status bit gets set.
For example, in order to enable DS3 Out of Frame interrupts, the following registers would need to be written:
Register bit
T3.RSRIE1.
GL.ISRIE.PISRIE
The following status registers bits will be set upon reception of OOF:
Register bit
T3.RSRL1.
PORT.ISR.
GL.ISR.PISR
10.2 Clocks
10.2.1 Line Clock Modes
10.2.1.1 Loop Timing Enabled
When loop timing is enabled (PORT.CR3.LOOPT), the transmit clock source is the same as the receive clock
source. The TCLKI pin is not used as a clock source. Because loop timing is enabled, the loopback functions (LLB,
PLB and DLB) do not cause the clock sources to switch when they are activated. The transmit and receive signal
pins can be timed to a single clock reference without concern about having the clock source change during
loopbacks.
BLOCK LATCHED
STATUS and
INTERRUPT
ENABLE
REGISTERS
SRIE bit
SRIE bit
SRIE bit
SRL bit
SRL bit
SRL bit
OOFL
FMSR
OOFIE
not only tells the user how to determine which event caused the interrupt, it also tells the user how to
Address
0x12C
0x012
Address
0x128
0x050
0x010
PORT INTERRUPT
STATUS
REGISTER
PORT.ISR bit
Value Written
0x0002
0x0010
Value Read
0x0002
0x0001
0x0010
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GLOBAL
INTERRUPT
STATUS REGISTER
and INTERRUPT
ENABLE REGISTER
GL.ISR.PISRn
GL.ISRIE.
PISRIEn
Note
DS3 Out of Frame
Framer Block Interrupt Active
Port Interrupt Active
Note
Unmask OOF interrupt
Unmask Port interrupts
DS3170 DS3/E3 Single-Chip Transceiver
INTERRUPTS
PORT
INTERRUPTS
GLOBAL
INT