DS3170 Maxim Integrated Products, DS3170 Datasheet - Page 151

no-image

DS3170

Manufacturer Part Number
DS3170
Description
Network Controller & Processor ICs DS3-E3 Single-Chip T ransceiver T3-E3 Fra
Manufacturer
Maxim Integrated Products
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS3170
Manufacturer:
DS
Quantity:
159
Part Number:
DS3170
Manufacturer:
DS
Quantity:
2 870
Part Number:
DS3170
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3170+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3170N
Manufacturer:
DS
Quantity:
3 283
Part Number:
DS3170N
Quantity:
737
Part Number:
DS3170N
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3170N+
Manufacturer:
MAXIM
Quantity:
301
Part Number:
DS3170N+
Manufacturer:
Maxim Integrated
Quantity:
10 000
Part Number:
DS3170N+T&R
Manufacturer:
Maxim Integrated
Quantity:
10 000
12.5 B3ZS/HDB3 Line Encoder/Decoder
12.5.1 Transmit Side Line Encoder/Decoder Register Map
The transmit side utilizes one register.
Table 12-14. Transmit Side B3ZS/HDB3 Line Encoder/Decoder Register Map
Address
12.5.1.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 4: Transmit Zero Suppression Encoding Disable (TZSD) – When 0, the B3ZS/HDB3 Encoder performs zero
suppression (B3ZS or HDB3) and AMI encoding. When 1, zero suppression (B3ZS or HDB3) encoding is disabled,
and only AMI encoding is performed.
Bit 3: Excessive Zero Insert Enable (EXZI) – When 0, excessive zero (EXZ) event insertion is disabled. When 1,
EXZ event insertion is enabled.
Bit 2: Bipolar Violation Insert Enable (BPVI) – When 0, bipolar violation (BPV) insertion is disabled. When 1,
BPV insertion is enabled.
Bit 1: Transmit Single Error Insert (TSEI) – This bit causes an error of the enabled type(s) to be inserted in the
transmit data stream if manual error insertion is disabled (MEIMS = 0). A 0 to 1 transition causes a single error to
be inserted. For a second error to be inserted, this bit must be set to 0, and back to 1. Note: If MEIMS is low, and
this bit transitions more than once between error insertion opportunities, only one error will be inserted.
Bit 0: Manual Error Insert Mode Select (MEIMS) – When 0, error insertion is initiated by the TSEI register bit.
When 1, error insertion is initiated by the transmit manual error insertion signal (TMEI). Note: If TMEI or TSEI is
one, changing the state of this bit may cause an error to be inserted.
08Ch
08Eh
15
--
--
0
7
0
LINE.TCR
Register
14
--
0
--
--
6
0
LINE.TCR
Line Transmit Control Register
08Ch
Line Transmit Control Register
Unused
Register Description
13
--
0
--
5
0
151 of 230
TZSD
12
--
0
4
0
EXZI
11
--
0
3
0
DS3170 DS3/E3 Single-Chip Transceiver
BPVI
10
--
0
2
0
TSEI
--
9
0
1
0
MEIMS
--
8
0
0
0

Related parts for DS3170