LX256EB-35FN484C Lattice, LX256EB-35FN484C Datasheet - Page 9
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LX256EB-35FN484C
Manufacturer Part Number
LX256EB-35FN484C
Description
Analog & Digital Crosspoint ICs E-Series, 256 I/O Switch Matrix, 2.5V, 3.5ns, Pb-Free
Manufacturer
Lattice
Datasheet
1.LX256EV-5FN484C.pdf
(75 pages)
Specifications of LX256EB-35FN484C
Maximum Dual Supply Voltage
2.7 V
Minimum Dual Supply Voltage
2.3 V
Mounting Style
SMD/SMT
Number Of Arrays
1
Operating Supply Voltage
2.5 V
Supply Type
Triple
Configuration
256 x 256
Package / Case
FPBGA-484
Data Rate
38 Gbps
Input Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Output Level
Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
Maximum Operating Temperature
+ 90 C
Minimum Operating Temperature
0 C
Product
Digital Crosspoint
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
The four data inputs to the 4:1 MUX come from the GRP. The output of this MUX connects to the output register. A
fast feedback path from the MUX to the GRP allows wider MUXes to be built. Table 2 summarizes the various MUX
sizes and delay levels.
Table 2. MUX Size Versus Internal Delay
Figure 3. ispGDX2 Family MRB
Control Array
The control array generates control signals for the 16 MRBs within a GDX Block. The true and complement forms
of 32 inputs from the GRP are available in the control array. The 20 NAND terms can use any or all of these inputs
to form the control array outputs. Two AND terms are combined with a NOR term to form Set/Reset and OE sig-
nals. Figure 4 illustrates the control array.
Signals
Global
Select
MUX
Control Array Signals
From GRP
To GRP
MUX Select
*Selected MRBs see Logic Signal Connection Table for details
4:1
Up to 16:1
Up to 64:1
Up to 188:1 (with ispGDX2-256)
4
Signals
Global
MUX Sizes
2-4
2
Control Array
GDX
4
2
FIFO Out*
Out_Reg(n-1)
Out_Reg(n+1)
from IN_Reg(n+1)
from IN_Reg(n-1)
S/R
CK
CE
from
from
Delay
S/R
6
CK
OE
CE
Levels of Internal GRP Delays
Global Resetb
Global Resetb
Three Levels
Four Levels
Two Levels
One Level
V
ClK
CE
D/L
CC
Reg/Latch
Set
V
CC
Input
CE
ClK
D/L
Set
Reg/Latch
CE
ClK
Reset
D/L
Reg/Latch
Set
Out
ispGDX2 Family Data Sheet
Q
Reset
OE
Reset
Q
Q
to IN_Reg(n-1)
to IN_Reg(n+1)
(FIFO, SERDES
or PLL)
Flags*
TOE
to Out_Reg(n-1)
to Out_Reg(n+1)