LX128C-5FN208C Lattice, LX128C-5FN208C Datasheet - Page 42

• Manufacturer Part Number: LX128C-5FN208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 1.8V, SERDES, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128C-5FN208C

• Maximum Dual Supply Voltage: 1.95 V
• Minimum Dual Supply Voltage: 1.65 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 1.8 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
sysHSI Block Timing
Figure 22 provides a graphical representation of the SERDES receiver input requirements. It provides guidance on
a number of input parameters, including signal amplitude and rise time limits, noise and jitter limits, and P and N
input skew tolerance.
Figure 22. Receive Data Eye Diagram Template (Differential)
The data pattern eye opening at the receive end of a link is considered the ultimate measure of received signal
quality. Almost all detrimental characteristics of a transmit signal and the interconnection link design result in eye
closure. This combined with the eye-opening limitations of the line receiver can provide a good indication of a link’s
ability to transfer error-free data.
Signal jitter is of special interest to system designers. It is often the primary limiting characteristic of long digital
links and of systems with high noise level environments. An interesting characteristic of the clock and data recovery
(CDR) portion of the ispGDX2 SERDES receiver is its ability to filter incoming signal jitter that is below the clock
recovery PLL bandwidth. For signals with high levels of low frequency jitter, the receiver can detect incoming data
error free, with eye openings significantly less than that shown in Figure 22.
sysHSI Block AC Specifications
f
f
f
1. f
2. f
CLK
SIN
SOUT
Symbol
SIN
SIN
2
2
(8B/10B and 10B/12B) 800Mbps limit applicable only to the fastest speed grade. Limit is 700Mbps for the lower speed grade.
and f
SOUT
Reference Clock Frequency
Serial Input
Serial Out
speeds are supported at V
Description
+/- 100 mV Single Ended
200 mV Differential
jt
TH
: Optimum Threshold Crossing Jitter
V
THD
CC
and V
SS:CAL
10B12B
SS:CAL
10B12B
8B10B
8B10B
Operating Frequency Ranges
Mode
LVDS
CCP
at 1.7V to 1.9V for ispGDX2C devices.
C
39
L
jt
= 5 pF, R
TH
f
Test Condition
CLK
with eo
with eo
with eo
with no jitter
L
Bit Time
= 100 Ohms,
SIN
SIN
SIN
eo
SIN
ispGDX2 Family Data Sheet
jt
TH
Min.
400
400
400
400
50
33
40
Max.
800
800
800
800
200
67
80
1
1
1
1
Units
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz