LX128EB-5FN208C Lattice, LX128EB-5FN208C Datasheet - Page 53

• Manufacturer Part Number: LX128EB-5FN208C
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 2.5V, 5ns, Pb-Free
• Manufacturer: Lattice

Specifications of LX128EB-5FN208C

• Maximum Dual Supply Voltage: 2.7 V
• Minimum Dual Supply Voltage: 2.3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 2.5 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Descriptions
Lattice Semiconductor
General Purpose
BKx_IOy
GCLK/CE0, GCLK/CE1, GCLK/CE2,
GCLK/CE3
SEL0, SEL1, SEL2
GOE0, GOE1, GOE2
RESETb
NC
GND
V
V
V
V
Testing and Programming
TMS
TCK
TDI
TDO
TOE
PLL Functions
PLL_FBKz
PLL_RSTz
CLK_OUTz
PLL_LOCKz
GND
V
FIFO Functions
FIFOy_DIN
FIFOy_DOUT
FIFOy_FIFORSTb
FIFOy_FULL
FIFOy_EMPTY
FIFOy_STRDb
SERDES Functions
HSImA_SINP, HSImB_SINP
HSImA_SINN, HSImB_SINN
HSImA_SOUTP, HSImB_SOUTP
HSImA_SOUTN, HSImB_SOUTN
HSImA_SYDT, HSImB_ SYDT
HSImA_RECCLK, HSImB_RECCLK
HSImA_CDRRSTb, HSImB_CDRRSTb
HSIm_CSLOCK
CC
CCJ
CCO
REF
CCP0,
P0,
x
x
V
GND
CCP1
w
Signal Names
P1
w
2
, SEL3
2
, GOE3
2
2
1
Input/Output – General purpose I/O number y in I/O Bank X.
Input – Global clock/clock enable inputs.
Input – Global MUX select inputs.
Input – Global output enable inputs.
Input – Global RESET signal (active low).
No connect.
GND – Ground.
VCC – The power supply pins for core logic.
VCC – The power supply for the JTAG logic.
VCC – The power supply pins for I/O Bank X.
Input – Defines the reference voltage for I/O Bank X.
Input – Test Mode Select input, used to control the 1149.1 state machine.
Input – Test Clock Input pin, used to clock the 1149.1 state machine.
Input – Test Data In pin, used to load data into device using 1149.1 state machine.
Output – Test Data Out pin used to shift data out of device using 1149.1.
Input – Test Output Enable pin. TOE tristates all I/O pins when driven low.
Input – Optional feedback input allows external feedback for PLL z.
Input – Optional input resets the M divider in PLL z.
Output – Optional clock output from PLL z (clock signal occupies the input path of
this I/O pad).
Output – Optional lock output from PLL z (lock signal occupies the input path of this
I/O pad).
GND – Ground for PLLs.
VCC – The power supply pins for PLLs.
Input – DATA IN Bit w of FIFO y.
Internal Signal – DATA OUT Bit w of FIFO y
Input – Reset input for FIFO y (active low).
Output – FULL flag for FIFO y.
Output – EMPTY flag for FIFO y.
Output – Start read (STRDb) flag for FIFO y.
Input – Positive sense serial input for sysHSI BLOCK m channel A, B.
Input – Negative (minus) sense serial input for sysHSI BLOCK m channel A, B.
Output – Positive sense serial output for sysHSI BLOCK m channel A, B.
Output – Negative (minus) sense serial output for sysHSI BLOCK m channel A, B.
Output – Symbol alignment detect for sysHSI BLOCK m channel A, B.
Internal Signal – Recovered clock for sysHSI BLOCK m channel A, B.
Input – Resets the CDR circuit of sysHSI BLOCK m channel A, B.
Output – LOCK output of the PLL associated with channel m.
50
Description
ispGDX2 Family Data Sheet