ISPGDX120A-7T176 Lattice, ISPGDX120A-7T176 Datasheet
ISPGDX120A-7T176
Specifications of ISPGDX120A-7T176
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ISPGDX120A-7T176 Summary of contents
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... Please refer to the table below for reference PCN and current product status. Product Line Ordering Part Number ispGDX80A-5T100 ispGDX80A ispGDX80A-7T100 ispGDX120A-5Q160 ispGDX120A-7Q160 ispGDX120A ispGDX120A-5T176 ispGDX120A-7T176 ispGDX160A-5B272 ispGDX160A-7B272 ispGDX160A ispGDX160A-5Q208 ispGDX160A-7Q208 5555 N.E. Moore Ct. Hillsboro, Oregon 97124-6421 Product Status Discontinued Phone (503) 268-8000 Internet: http://www ...
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... Outputs Tri-state During Power-up (“Live Insertion” Friendly) Copyright © 2002 Lattice Semiconductor Corporation. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. ...
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... Vcc and I/O pins must still be met. For additional information, an application note about using Lattice de- vices in hot swap environments can be downloaded from the Lattice web site at www.latticesemi.com. ispGDX DEVICE ispGDX80A ispGDX120A ...
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... I/O pins. Boundary Scan test is supported by dedicated registers at each I/O pin. The in-system programming process uses either a Bound- ary Scan based or Lattice ISP protocol. The programming protocol is selected by the BSCAN/ispEN pin as de- scribed later. The various I/O pin sets are also shown in the block diagram below ...
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... Therefore, there is a need for a flexible means to inte- grate these on-board data path functions in an analogous way to programmable logic’s solution to control logic integration. Lattice’s ispLSI High-Density PLDs make an ideal control logic complement to the ispGDX in-system programmable data path devices as shown below. ...
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... The UES information is accessible through the XCVR I/OA I/OB boundary scan or Lattice ISP programming port via a specific command. This information can be read even OEA OEB when the security cell is programmed. Security Bit The ispGDX Family includes a security bit feature that prevents reading the device program once set ...
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Absolute Maximum Ratings Supply Voltage V ................................. -0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to ...
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Switching Test Conditions Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions TEST CONDITION A 160Ω Active High B ...
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External Timing Parameters TEST 1 PARAMETER # COND Data Propagation Delay from any I/O pin to any I/O pin sel Data Propagation Delay from MUXsel Inputs to any Output f max(ext) – 3 ...
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Internal Timing Parameters 2 PARAMETER # Inputs t 21 Input Buffer Delay io GRP t 22 GRP Delay grp MUX t 23 I/O Cell MUX A/B/C/D Data Delay muxd t 24 I/O Cell MUX A/B/C/D Data Select muxs Register t ...
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Switching Waveforms VALID INPUT MUXSEL (I/O INPUT) t sel DATA (I/O INPUT) VALID INPUT t pd COMBINATORIAL I/O OUTPUT Combinatorial Output OE (I/O INPUT) t dis COMBINATORIAL I/O OUTPUT I/O Output Enable/Disable CLK (I/O INPUT) Clock Width ...
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Development System The ispLEVER Development System supports ispGDX design using a VHDL or Verilog language syntax. From creation to in-system programming, the ispLEVER sys- tem is an easy-to-use, self-contained design tool. Features • VHDL and Verilog Synthesis Support Available ...
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... I/O A39.. A0, I/O D39 .. D20, SDO/TDO Table 4. ispGDX Device ID Codes DEVICE 8-BIT ISP ID ispGDX80A 0111 0111 ispGDX120A 0111 1000 ispGDX160/A 0111 1001 Boundary Scan The ispGDXV/VA devices provide IEEE1149.1a test capability and ISP programming through a standard Boundary Scan Test Access Port (TAP) interface. ...
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Figure 7. Boundary Scan I/O Register Cell SCANIN M (from U previous X cell Shift DR Figure 8. Boundary Scan State Machine Test-Logic-Reset 1 0 Run-Test/Idle 0 TCK TMS or TDI TDO tsu = ...
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... Input Pins – Dedicated clock input pins. Each pin can drive any or all I/O cell registers. BSCAN/ispEN Input Pin – When HIGH, this pin enables the Boundary Scan Test and Programming Interface. When LOW, this pin enables the Lattice ISP protocol for programming and tristates all I/O pins, except those used for the programming interface. TDI/SDI Input/Input Pin – ...
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I/O Locations: ispGDX160A 208 272 Signal PQFP BGA Signal PQFP BGA I/O A32 I I I/O A33 I I/O A34 I I/O A35 I I/O ...
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Signal Configuration: ispGDX160A ispGDX160A 272-Ball BGA Signal Diagram I/O I/O I I/O I/O I D11 I/O ...
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Pin Configuration: ispGDX160A ispGDX160A 208-Pin PQFP (with Heat Spreader) Pinout Diagram Control Data — 1 VCC CLK I I MUXsel1 I MUXsel2 I — GND CLK ...
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... 43, 44, 45, 46, 61, 62, 87, 88, 89, 90, 130, 131, 55, 56, 120, 137 132, 133, 134, 151, 175, 176 1. NC pins are not to be connected to any active signals, VCC or GND. I/O Locations: ispGDX120A 176 160 Signal TQFP PQFP Signal ...
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... Pin Configuration: ispGDX120A ispGDX120A 176-Pin TQFP Pinout Diagram Control Data 1 1 — NC — — VCC 4 CLK I I MUXsel1 I MUXsel2 I — GND 8 9 CLK I I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I MUXsel2 I — GND 18 CLK I — VCC I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I MUXsel2 ...
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... Pin Configuration: ispGDX120A ispGDX120A 160-Pin PQFP Pinout Diagram Control Data — VCC 1 CLK I I MUXsel1 I MUXsel2 I — GND 6 CLK I I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I MUXsel2 I — GND CLK I — VCC I MUXsel1 I MUXsel2 I CLK I I MUXsel1 I MUXsel2 I — GND 26 CLK I I MUXsel1 ...
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Signal Locations: ispGDX80A Signal 100-Pin TQFP Y1/TOE RESET 89 BSCAN/ispEN 35 TDI/SDI 39 TCK/SCLK 36 TMS/MODE 86 TDO/SDO 85 GND 6, 18, 29, 45, 56, 68, 79, 95 VCC 12, 37, 62, 88 I/O Locations: ispGDX80A Signal ...
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Pin Configuration: ispGDX80A ispGDX80A 100-Pin TQFP Pinout Diagram Control Data CLK I I MUXsel1 I MUXsel2 I CLK I GND 6 — I I/O A6 MUXsel1 ...
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... Q208 = PQFP (with Heat Spreader) T176 = TQFP Q160 = PQFP B272 = BGA T100 = TQFP COMMERCIAL ORDERING NUMBER ispGDX160A-5Q208 ispGDX160A-5B272 ispGDX160A-7Q208 ispGDX160A-7B272 ispGDX120A-5T176 ispGDX120A-5Q160 ispGDX120A-7T176 ispGDX120A-7Q160 ispGDX80A-5T100 ispGDX80A-7T100 23 0212/ispGDX PACKAGE 208-Pin PQFP 272-Ball BGA 208-Pin PQFP 272-Ball BGA 176-Pin TQFP 160-Pin PQFP 176-Pin TQFP ...