LX128B-5F208C Lattice, LX128B-5F208C Datasheet - Page 51

• Manufacturer Part Number: LX128B-5F208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 2.5V, SERDES, 5ns
• Manufacturer: Lattice

Specifications of LX128B-5F208C

• Maximum Dual Supply Voltage: 2.7 V
• Minimum Dual Supply Voltage: 2.3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 2.5 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Power Consumption (Continued)
Power consumption in the ispGDX2 family is the sum of three components:
Where:
I
plied by the V
The I
be derived from the equations below.
Where:
Note: For further information about the use of these coefficients, refer to Technical Note TN1034, Power Estimation
in the ispGDX2 Family.
I
TOTAL
HSI
CC-TOTAL
can also be determined by calculating I
CCP
is sensitive to operating conditions and the program in the device, the actual current should be verified.
I
I
I
F
F
F
I
I
I
I
I
CORE
PLL
HSI
HSI
CCP
PLL_A
HSI_A
CC-TOTAL
VCO
RX
TX
is supplied through V
estimates are based on typical conditions. These values are for estimates only. Since the value of I
:
:
: sysClock PLL VCO Frequency in MHz
CCP0
: HSI Analog Portion Current
: PLL Analog Portion Current
= I
= Blank chip background current
= I
= [K
= [(K
= I
= [(K
sysHSI Receiver Serial Data Rate
sysHSI Transmitter Serial Data Rate
= I
= [(K
= I
= [(K
+ K
+ (K
+ [(K
+ (K
+[(K
+ (K
+ [(K
+ (K
= I
DC
PLL_D
RX
HSI_D
PLL_A
and V
PLLD
PLLD
RXD
RXD
PLLA
CORE
REF
+ I
+ I
IN
TXD
RXA
TXA
TXA
TXD
RXA
REF
TX
+ I
* Number of inputs + K
+ I
+ I
CCP1
* F
+ K
* F
* Number of Banks with V
* F
+ K
* F
* F
* F
* F
+ I
+ K
HSI_A
* F
HSI_A
PLL_A
VCO
RX
+ I
RXA
VCO
TX
TX
TX
PLLA
RX
PLL
.
RX
TXA
CCP0
IN
+ I
) * Number of Transmitter Channels]
) * Number of Transmitter Channels]
) * Number of Receiver Channels
+ I
) * F
) * Number of Receiver Channels
* Number of PLLs used] + [K
) * Number of PLLs used]
+ I
) * F
RXSTBY
) * F
TXSTBY
HSI
and V
RX
VCO
TX
(I
+ I
CC-TOTAL
)* Number of Receiver Channels
+ I
) * Number of Transmitter Channels]
] * Number of PLLs used
CCP1
RXSTBY
TXSTBY
HSI_D
CORE
pins for PLL and sysHSI analog portion. The equation for I
, the current supplied by the V
] * Number of Receiver Channels
combines current supplied via V
] * Number of Transmitter Channels
REF
) * Average Input Switching Frequency (MHz)
active
48
PLLA
* F
VCO
* Number of PLLs used]
ispGDX2 Family Data Sheet
CC
CC
pin, and I
pins and V
HSI_A,
CCP
the current sup-
pins)
CCP
can
CC-