CS8900A-CQ3R Cirrus Logic Inc, CS8900A-CQ3R Datasheet - Page 2

• Manufacturer Part Number: CS8900A-CQ3R
• Description: Ethernet ICs IC 10Mbps Ethernet Controller 3.3V
• Manufacturer: Cirrus Logic Inc

Specifications of CS8900A-CQ3R

• Ethernet Connection Type: 10Base- 2, 10Base- 5, 10Base- F, 10Base- T
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Standard Supported: IEEE 802.3
• Data Rate: 10 Mbps
• Maximum Operating Temperature: + 70 C
• Package / Case: LQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE OF CONTENTS
2
1.0 INTRODUCTION ......................................................................................................................8
2.0 PIN DESCRIPTION
3.0 FUNCTIONAL DESCRIPTION ...............................................................................................17
1.1 General Description ...........................................................................................................8
1.2 System Applications ..........................................................................................................8
1.3 Key Features and Benefits ..............................................................................................10
3.1 Overview .........................................................................................................................17
3.2 ISA Bus Interface ............................................................................................................18
3.3 Reset and Initialization ....................................................................................................19
3.4 Configurations with EEPROM .........................................................................................21
1.1.1 Direct ISA-Bus Interface .......................................................................................8
1.1.2 Integrated Memory ...............................................................................................8
1.1.3 802.3 Ethernet MAC Engine .................................................................................8
1.1.4 EEPROM Interface ...............................................................................................8
1.1.5 Complete Analog Front End .................................................................................8
1.2.1 Motherboard LANs ...............................................................................................8
1.2.2 Ethernet Adapter Cards ........................................................................................9
1.3.1 Very Low Cost ....................................................................................................10
1.3.2 High Performance ...............................................................................................10
1.3.3 Low Power and Low Noise .................................................................................10
1.3.4 Complete Support ...............................................................................................10
3.1.1 Configuration ......................................................................................................17
3.1.2 Packet Transmission ..........................................................................................17
3.1.3 Packet Reception ...............................................................................................17
3.2.1 Memory Mode Operation ....................................................................................18
3.2.2 I/O Mode Operation ............................................................................................18
3.2.3 Interrupt Request Signals ...................................................................................18
3.2.4 DMA Signals .......................................................................................................18
3.3.1 Reset ..................................................................................................................19
3.3.2 Allowing Time for Reset Operation .....................................................................20
3.3.3 Bus Reset Considerations ..................................................................................20
3.3.4 Initialization .........................................................................................................20
3.4.1 EEPROM Interface .............................................................................................21
3.4.2 EEPROM Memory Organization .........................................................................21
3.4.3 Reset Configuration Block ..................................................................................21
3.4.4 Groups of Configuration Data .............................................................................23
3.4.5 Reset Configuration Block Checksum ................................................................24
3.4.6 EEPROM Example .............................................................................................24
3.4.7 EEPROM Read-out ............................................................................................24
3.3.1.1 External Reset, or ISA Reset ...............................................................19
3.3.1.2 Power-Up Reset ..................................................................................19
3.3.1.3 Power-Down Reset ..............................................................................19
3.3.1.4 EEPROM Reset ...................................................................................19
3.3.1.5 Software Initiated Reset .......................................................................19
3.3.1.6 Hardware (HW) Standby or Suspend ..................................................19
3.3.1.7 Software (SW) Suspend ......................................................................19
3.4.3.1 Reset Configuration Block Structure ....................................................22
3.4.3.2 Reset Configuration Block Header ......................................................22
3.4.3.3 Determining the EEPROM Type ..........................................................23
3.4.3.4 Checking EEPROM for presence of Reset Configuration Block ..........23
3.4.3.5 Determining Number of Bytes in the Reset Configuration Block .........23
3.4.4.1 Group Header ......................................................................................23
.............................................................................................................12
CIRRUS LOGIC PRODUCT DATASHEET
Crystal LAN™ Ethernet Controller
CS8900A
DS271F5