LX128EB-5F208C Lattice, LX128EB-5F208C Datasheet - Page 13

• Manufacturer Part Number: LX128EB-5F208C
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 2.5V, 5ns
• Manufacturer: Lattice

Specifications of LX128EB-5F208C

• Maximum Dual Supply Voltage: 2.7 V
• Minimum Dual Supply Voltage: 2.3 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 2.5 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
N divider is used to multiply the clock signal. The K divider is used to provide a divided clock frequency of the adja-
cent PLL. This output can be routed to the global clock net. The V divider is used to provide lower frequency output
clocks, while maintaining a stable, high frequency output from the PLL’s VCO circuit. The PLL also has a delay fea-
ture that allows the output clock to be advanced or delayed to improve set-up and clock-to-out times for better per-
formance. For more information on the PLL, please refer to Lattice technical note number TN1003, sysCLOCK PLL
Design and Usage Guidelines .
Figure 6. sysCLOCK PLL
There are four global clock networks routed to each MRB block. These global clocks, CLK0-3, can either be gener-
ated by the PLL circuits or supplied externally. External clock pins can be configured as single-ended or differential
(LVDS) input. Figure 7 illustrates how the sysCLOCK PLL inputs and outputs can be routed to the I/O pins or gen-
eral routing. Figure 10 shows the clock network for the ispGDX2-256 and Figure 8 shows the clock networks for
ispGDX2-128 and ispGDX2-64. The Reset (0) pin from the Control Array of selected GDX Blocks can be pro-
grammed to reset the M Divider of the PLLs. This provides a means for generating the reset signal internally.
Table 5 details which GDX Block provides reset to the PLLs.
Table 5. Internal Reset Input of the PLL (M Divider)
ispGDX2-256
ispGDX2-128
ispGDX2-64
PLL_FBK
CLK_IN
PLL_RST
Input Clock
(M) Divider
1 to 32
GDX Block 5A
GDX Block 2A
GDX Block 0A
PLL0
Programmable
Programmable
--------------------
Divider (N)
Feedback
X 1 to 32
+Delay
-Delay
PLL (n)
GDX Block 7B
PLL1
10
—
—
Post-scalar
(V) Divider
1, 2, 4, 8,
16, 32
Clock (K)
Divider
2, 4, 8,
16, 32
GDX Block 1A
GDX Block 0A
GDX Block 1B
PLL2
ispGDX2 Family Data Sheet
To Adjacent_PLL
Adjacent_PLL
From
Clock Net
GDX Block 3B
PLL_LOCK
CLK_OUT
PLL3
—
—