LX128EC-5F208C Lattice, LX128EC-5F208C Datasheet - Page 24

• Manufacturer Part Number: LX128EC-5F208C
• Description: Analog & Digital Crosspoint ICs E-Series, 128 I/O Switch Matrix, 1.8V, 5ns
• Manufacturer: Lattice

Specifications of LX128EC-5F208C

• Maximum Dual Supply Voltage: 1.95 V
• Minimum Dual Supply Voltage: 1.65 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 1.8 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2 Family Data Sheet
IEEE 1149.1-Compliant Boundary Scan Testability
All ispGDX2 devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows func-
tional testing of the circuit board on which the device is mounted through a serial scan path that can access all crit-
ical logic notes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto
test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked
into a board-level serial scan path for more board-level testing. The test access port has its own supply voltage that
can operate with LVCMOS3.3, 2.5 and 1.8 standards.
sysIO Quick Configuration
To facilitate the most efficient board test, the physical nature of the I/O cells must be set before running any continu-
ity tests. As these tests are fast, by nature, the overhead and time that is required for configuration of the I/Os'
physical nature should be minimal so that board test time is minimized. The ispGDX2 family of devices allows this
by offering the user the ability to quickly configure the physical nature of the sysIO cells. This quick configuration
takes milliseconds to complete, whereas it takes seconds for the entire device to be programmed. Lattice's
ispVM™ System programming software can either perform the quick configuration through the PC parallel port, or
can generate the ATE or test vectors necessary for a third-party test system.
IEEE 1532-Compliant In-System Programming
In-system programming of devices provides a number of significant benefits including rapid prototyping, lower
inventory levels, higher quality and the ability to make in-field modifications. All ispGDX2 devices provide In-System
Programming (ISP) capability through their Boundary Scan Test Access Port. This capability has been imple-
mented in a manner that ensures that the port remains compliant to the IEEE 1532 standard. By using IEEE 1532
as the communication interface through which ISP is achieved, designers get the benefit of a standard, well defined
interface.
The ispGDX2 devices can be programmed across the commercial temperature and voltage range. The PC-based
Lattice software facilitates in-system programming of ispGDX2 devices. The software takes the JEDEC file output
produced by the design implementation software, along with information about the scan chain, and creates a set of
vectors used to drive the scan chain. The software can use these vectors to drive a scan chain via the parallel port
of a PC. Alternatively, the software can output files in formats understood by common automated test equipment.
This equipment can then be used to program ispGDX2 devices during the testing of a circuit board.
Security Scheme
A programmable security scheme is provided on the ispGDX2 devices as a deterrent to unauthorized copying of
the array configuration patterns. Once programmed, this scheme prevents readback of the programmed pattern by
a device programmer, securing proprietary designs from competitors. The security scheme also prevents program-
ming and verification. The entire device must be erased in order to reset the security scheme.
Hot Socketing
The ispGDX2 devices are well suited for those applications that require hot socketing capability. Hot socketing a
device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without
being damaged. Additionally, it requires that the effects of the powered-down device be minimal on active signals.
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