LX128C-32F208C Lattice, LX128C-32F208C Datasheet - Page 65

• Manufacturer Part Number: LX128C-32F208C
• Description: Analog & Digital Crosspoint ICs 128 I/O Switch Matrix, 1.8V, SERDES, 3.2ns
• Manufacturer: Lattice

Specifications of LX128C-32F208C

• Maximum Dual Supply Voltage: 1.95 V
• Minimum Dual Supply Voltage: 1.65 V
• Mounting Style: SMD/SMT
• Number Of Arrays: 1
• Operating Supply Voltage: 1.8 V
• Supply Type: Triple
• Configuration: 128 x 128
• Package / Case: FPBGA-208
• Data Rate: 21 Gbps
• Input Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Output Level: Bus LVDS, LVCMOS, LVDS, LVPECL, LVTTL
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Product: Digital Crosspoint
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispGDX2-256 Logic Signal Connections (Continued)
BK2_IO10
BK2_IO11
GND
BK2_IO12
BK2_IO13
BK2_IO14
BK2_IO15
BK2_IO16
BK2_IO17
BK2_IO18
BK2_IO19
GND
BK2_IO20/
PLL_FB3
BK2_IO21/
VREF2
BK2_IO22
BK2_IO23
BK2_IO24
BK2_IO25
BK2_IO26
BK2_IO27
BK2_IO28
BK2_IO29
BK2_IO30
BK2_IO31
BK3_IO1
BK3_IO2
BK3_IO3
GND
BK3_IO4
BK3_IO5
BK3_IO6
BK3_IO7
BK3_IO8
GND
TCK
GOE2
BK3_IO0
BK3_IO9
BK3_IO10/
VREF3
BK3_IO11
GND
BK3_IO12
BK3_IO13
BK3_IO14/
PLL_RST3
Signal
Name
sysIO
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
-
-
Pair/Polarity
LVDS
37N
37P
38N
38P
39N
39P
40N
40P
41N
41P
42N
42P
43N
43P
44N
44P
45N
45P
46N
46P
47N
47P
48P
48N
49P
49N
50P
50N
51P
51N
52P
52N
53P
53N
54P
54N
55P
-
-
-
-
-
-
-
Block MRB
GDX
3A
3A
3A
3A
3A
3A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
2A
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
3B
-
-
-
-
-
-
-
7
7
7
7
7
7
10
11
12
13
14
15
10
11
12
13
14
15
10
11
12
13
14
0
1
2
3
4
5
6
7
8
9
0
1
2
3
4
5
6
7
8
9
-
-
-
-
-
-
-
HSI3A_CDRRSTb
HSI2A_CDRRSTb
HSI3B_CDRRSTb
FIFO2A_STRDb
FIFO3A_STRDb
FIFO3B_STRDb
SERDES Mode
HSI2A_SOUTN
HSI3B_SOUTN
HSI3A_SOUTN
HSI3A_SOUTP
HSI2A_SOUTP
HSI2_CSLOCK
HSI3B_SOUTP
HSI3A_SYDT
HSI2A_SYDT
HSI3B_SYDT
HSI2A_SINN
HSI3B_SINN
HSI2A_SINP
HSI3B_SINP
I/O Pin
Note 4
Note 4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
1
62
5
5
5
6
6
6
HSI3A_RXD7/TXD7
HSI3A_RXD8/TXD8
HSI3A_RXD9/TXD9
HSI2A_RXD0/TXD0
HSI2A_RXD1/TXD1
HSI2A_RXD2/TXD2
HSI2A_RXD3/TXD3
HSI2A_RXD4/TXD4
HSI2A_RXD5/TXD5
HSI2A_RXD6/TXD6
HSI2A_RXD7/TXD7
HSI2A_RXD8/TXD8
HSI2A_RXD9/TXD9
HSI3B_RXD0/TXD0
HSI3B_RXD1/TXD1
HSI3B_RXD2/TXD2
HSI3B_RXD3/TXD3
HSI3B_RXD4/TXD4
HSI3B_RXD5/TXD5
HSI3B_RXD6/TXD6
HSI3B_RXD7/TXD7
HSI3B_RXD8/TXD8
HSI3B_RXD9/TXD9
HSI3A_RECCLK
HSI2A_RECCLK
HSI3B_RECCLK
HSI3B_RECCLK
SERDES Mode
HSI2A_SYDT
HSI3B_SYDT
I/O Cell
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2
5
5
ispGDX2 Family Data Sheet
FIFO3A_DIN7/DOUT7
FIFO3A_DIN8/DOUT8
FIFO3A_DIN9/DOUT9
FIFO2A_DIN0/DOUT0
FIFO2A_DIN1/DOUT1
FIFO2A_DIN2/DOUT2
FIFO2A_DIN3/DOUT3
FIFO2A_DIN4/DOUT4
FIFO2A_DIN5/DOUT5
FIFO2A_DIN6/DOUT6
FIFO2A_DIN7/DOUT7
FIFO2A_DIN8/DOUT8
FIFO2A_DIN9/DOUT9
FIFO3B_DIN0/DOUT0
FIFO3B_DIN1/DOUT1
FIFO3B_DIN2/DOUT2
FIFO3B_DIN3/DOUT3
FIFO3B_DIN4/DOUT4
FIFO3B_DIN5/DOUT5
FIFO3B_DIN6/DOUT6
FIFO3B_DIN7/DOUT7
FIFO3B_DIN8/DOUT8
FIFO3B_DIN9/DOUT9
FIFO3A_FIFORSTb
FIFO2A_FIFORSTb
FIFO3B_FIFORSTb
FIFO3A_EMPTY
FIFO2A_EMPTY
FIFO Mode I/O
FIFO2A_FULL
FIFO3B_FULL
Cell/Pin
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
fpBGA
GND
GND
GND
GND
GND
G17
G15
G14
K16
H20
G21
G20
G22
F21
H18
E21
E22
D22
H17
H16
E19
D20
D21
B19
C19
E17
D18
A19
A18
D17
D16
C18
B18
B17
A17
A16
484
J16
J19
F22
F20
F19
F18
F15
F14