COM20019ILJPTR SMSC, COM20019ILJPTR Datasheet - Page 59

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COM20019ILJPTR

Manufacturer Part Number
COM20019ILJPTR
Description
Network Controller & Processor ICs Arcnet (ANSI 878.1) Controllr 2k x 8 Ram
Manufacturer
SMSC
Datasheet

Specifications of COM20019ILJPTR

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
SMSC COM20019I
Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
nRESET
XTAL1
Note*: T
Note**: T
Note***: When the power is turned on, t1 is measured from stable XTAL
Note*: t4 and t5 are applied to crystal oscillaton.
t1
t2
t5
t1
t2
t3
t4
nINTR
oscillation after V
XTL
DR
4.0V
nRESET Pulse Width***
nINTR High to Next nINTR Low
Input Clock High Time
Input Clock Low Time
Input Clock Period
Input Clock Frequency*
Frequency Accuracy*
is period of Data Rate (i.e. at 312.5 Kbps, T
is period of external XTAL oscillation frequency.
Parameter
Parameter
Figure 8.12 - TTL INPUT TIMING ON XTAL1 PIN
Figure 8.13 - RESET AND INTERRUPT TIMING
DD
t1
t1
was over 4.5V.
1.0V
DATASHEET
t2
EF = 0
EF = 1
Page 59
t2
DR
= 3200 nS)
T
5T
-200
4T
min
DR
min
20
20
50
10
t3
XTL
**/2
XTL
*
*
typ
typ
100
max
200
max
20
50% of V
units
MHz
ppm
units
nS
nS
nS
DD
Rev. 09-25-07

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