ZL30106QDG Zarlink, ZL30106QDG Datasheet - Page 16

• Manufacturer Part Number: ZL30106QDG
• Description: SONET/SDH/PDH Network Interface 64-Pin TQFP
• Manufacturer: Zarlink

Specifications of ZL30106QDG

• Package: 64TQFP
• Power Supply Type: Analog
• Typical Supply Current: 68(Max) mA
• Typical Operating Supply Voltage: 1.8|3.3 V
• Minimum Operating Supply Voltage: 1.62 V
• Maximum Operating Supply Voltage: 3.63 V

3.3
The TIE Circuit eliminates phase transients on the output clock that may occur during reference switching or the
recovery from Holdover mode to Normal mode.
On recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the
TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the
selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual
reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL
minimizes the phase transient it experiences when it recovers from Holdover mode.
The delay value can be reset by setting the TIE Corrector Circuit Clear pin (TIE_CLR) low for at least 15 ns. This
results in a phase alignment between the input reference signal and the output clocks and frame pulses as shown
in Figure 23. The speed of the phase alignment correction is limited by the loop filter bandwidth. Convergence is
always in the direction of least phase travel. TIE_CLR can be kept low continuously. In that case the output clocks
will always align with the selected input reference. This is illustrated in Figure 9.
Time Interval Error (TIE) Corrector Circuit
REF
frequency
REF
REF_SYNC
frequency
REF_SYNC
Figure 8 - REF_SYNC Monitor Circuit
Zarlink Semiconductor Inc.
ZL30106
REF_SYNC
REF_SYNC
Frequency
Detector
Monitor
Ratio
16
to DPLL
Data Sheet