ZL30310GKG Zarlink, ZL30310GKG Datasheet

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ZL30310GKG

Manufacturer Part Number
ZL30310GKG
Description
Combined Synchronous Ethernet 256-Pin TEBGA
Manufacturer
Zarlink
Datasheet

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ZL30310GKG
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Part Number:
ZL30310GKG2
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A full Design Manual is available to qualified customers.
To register, please send an email to
TimingandSync@Zarlink.com.
Features
Recovers and transmits network synchronization
over Ethernet, IP and MPLS Networks
Simultaneously supports both the Synchronous
Ethernet and the IEEE1588 industry standard timing
protocols
Capable of server, client and repeater operation
Integrates two separate digital phase locked loops,
with hitless switching between packet and electrical
clock references
Primary DPLL meets Stratum 3E quality
Targeted for synchronization distribution to better
than ITU-T G.8261, G.823, G.824 and ANSI T1.101
synchronization interface standards
Average frequency accuracy better than ±10 ppb
Aligns to a low frequency input signal at server
(e.g., 1 Hz) with targeted accuracy better than ±1 μs
Recovers clocks from two independent servers, with
hitless switching between packet streams for
redundancy
Supports holdover if the server stream is lost
Accepts eight input references, and up to three
associated low frequency alignment or framing pulses
Generates up to four separate output clocks at
frequencies between 8 kHz and 100 MHz
(G M II/T B I/M II/R M II)
N e tw o rk I/F
P o rt M 2
sy n c 0
sy n c 1
sy n c 2
re f0
re f1
re f2
re f3
re f4
re f5
re f6
re f7
o s c i
o s c o
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
M a s te r
In p u t P o rts
O s c
M o n ito rs
M A C
R e f
Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved.
&
Figure 1 - ZL30310 Functional Block Diagram
re f
s y n c
re f
Zarlink Semiconductor Inc.
n
m
T im e s ta m p E n g in e
n
E th e rn e t B rid g e
S tra tu m 3 E
D P L L 1
D P L L 2
1
Combined Synchronous Ethernet and
Applications
IEEE1588 Network Synchronization
Generates two separate Synchronous Ethernet
clocks to drive industry standard Ethernet PHY
devices at either 25 MHz or 125 MHz
Fully configurable solution, enabling performance
to be tailored to application/network requirements
Two independently configurable MAC interfaces,
supporting MII, RMII, GMII and TBI standards
Wire-speed Ethernet Bridge pass through function
between the MAC interfaces
Synchronous serial control interface
Full demonstration & evaluation platform available
IEEE 1588 and Synchronous Ethernet timing
GSM and UMTS air interface synchronization
over a packet network
Circuit Emulation Services over Packets
IP-PBX and VoIP Gateways
Video Conferencing
Broadband Video Distribution
ZL30310GKG
ZL30310GKG2
Ordering Information
S y n th e s iz e r
S y n th e s iz e r
-40°C to +85°C
M A C
A P L L
P 0
P 1
256 TEPBGA, 17 x 17 mm
256 TEPBGA, 17 x 17 mm
S S I
T o P
P L L
P o rt M 1
P ro c e s s o r I/F
(G M II/T B I/M II/R M II)
R e g is te r
A cc e s s I/F
E T H _ C L K 0
E T H _ C L K 1
p 0 _ c lk 0
p 0 _ c lk 1
p 0 _ fp 0
p 0 _ fp 1
p 1 _ c lk 0
p 1 _ c lk 1
ZL30310
Data Sheet
June 2009

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ZL30310GKG Summary of contents

Page 1

... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2009, Zarlink Semiconductor Inc. All Rights Reserved. Combined Synchronous Ethernet and IEEE1588 Network Synchronization Ordering Information ZL30310GKG ZL30310GKG2 -40°C to +85°C • Generates two separate Synchronous Ethernet clocks to drive industry standard Ethernet PHY devices at either 25 MHz or 125 MHz • ...

Page 2

... There are two main ways to enable synchronization over a packet network, synchronizing the packet network itself the Synchronous Ethernet approach, or distributing the timing using the packets as in Zarlink’s Timing over Packet (ToP) technology. The two techniques can also be combined to provide a very powerful hybrid solution. ...

Page 3

... Using this information, clients are able to align their own timebase with that of the server client, the Zarlink device can track two independent servers, and determine which one is providing the best time reference. If either the primary reference or the network between the server and client fails, the device can switch to the alternative reference without introducing a phase discontinuity ...

Page 4

... Zarlink Semiconductor 2006 All rights reserved ISSUE CDCA ACN 24Aug06 DATE APPRD. Package Code Previous package codes ...

Page 5

... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...

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