ZL30310GKG Zarlink, ZL30310GKG Datasheet - Page 2

• Manufacturer Part Number: ZL30310GKG
• Description: Combined Synchronous Ethernet 256-Pin TEBGA
• Manufacturer: Zarlink

Description
Network infrastructures are gradually converging onto a packet-based architecture. With this convergence, there
are a significant number of synchronous applications that require accurate timing to be distributed over the packet
networks. Examples of precision timing sensitive applications that need the transport of synchronization over
packet networks include transport of TDM over packet networks, connections to 2 G and 3 G cellular base stations,
Voice over IP, IP PBXs, video-conferencing and broadband video.
There are two main ways to enable synchronization over a packet network, synchronizing the packet network itself,
as in the Synchronous Ethernet approach, or distributing the timing using the packets as in Zarlink’s Timing over
Packet (ToP) technology. The two techniques can also be combined to provide a very powerful hybrid solution.
Synchronous Ethernet delivers a very accurate frequency reference, but doesn’t address phase and time
synchronization. ToP can be used to supplement the excellent frequency distribution of Synchronous Ethernet with
accurate phase and time information. Alternatively, ToP can be used to extend the reach of the Synchronous
Ethernet reference across an asynchronous network, such as a LAN connected to a synchronous WAN.
Zarlink has combined both methods into a single device. The ZL30310 incorporates an extremely low-jitter
frequency synthesizer, capable of generating all the frequencies required for Synchronous Ethernet operation,
together with Zarlink’s patent-pending Timing over Packet (ToP) technology based on the industry-standard
IEEE1588
supports the distribution of time, phase and frequency across both layer 2 and layer 3 networks, using both
Synchronous Ethernet and IEEE1588 protocols, either alone or in combination.
The ZL30310 is a member of a family of footprint-compatible devices offering the full range of features required for
timing and synchronization across the packet network. These devices facilitate design of a flexible card that can be
upgraded as required by simply placing another member of the same family.
The family members include:
ZL30310
ZL30312
ZL30314
ZL30316
ZL30320
ZL30321
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“PTP” (Precision Time Protocol). Not only can it function as a fully-featured Digital PLL, it also
Combined IEEE1588
and GR-253 SONET and G.813 quality phase locked loop for timing card applications, plus a second
independent PLL for rate conversion or generation of additional derived clocks.
Combined IEEE1588
GR-253 SEONET and G.813 quality phase locked loop for timing card applications, plus a second
independent PLL for rate conversion or generation of additional derived clocks.
Combined IEEE1588
G.813 Option 1 quality phase locked loop for timing card applications, plus a second independent PLL
for rate conversion or generation of additional derived clocks.
Combined IEEE1588
locked loops for line card applications
Combined IEEE1588
Synchronous Ethernet line card device in a ToP compatible footprint, containing two independent DPLLs
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ToP and Synchronous Ethernet, coupled with a GR-1244 Stratum 3E/3/4/4E
ToP and Synchronous Ethernet, coupled with a GR-1244 Stratum 3/4/4E and
ToP and Synchronous Ethernet, coupled with a GR1244 Stratum 3/4/4E and
ToP and Synchronous Ethernet, coupled with two independent, flexible phase
ToP and Synchronous Ethernet for line card applications
Zarlink Semiconductor Inc.
ZL30310
2
Data Sheet