AD669BRZ Analog Devices Inc, AD669BRZ Datasheet - Page 11

• Manufacturer Part Number: AD669BRZ
• Description: DAC 1-CH R-2R/Current Steering 16-Bit 28-Pin SOIC W
• Manufacturer: Analog Devices Inc
• Series: DACPORT®r

Specifications of AD669BRZ

• Package: 28SOIC W
• Resolution: 16 Bit
• Conversion Rate: 167 KSPS
• Architecture: R-2R|Current Steering
• Digital Interface Type: Parallel
• Number Of Outputs Per Chip: 1
• Output Type: Voltage
• Signal To Noise Ratio: 83(Min) dB
• Full Scale Error: ±0.1 %FSR
• Integral Nonlinearity Error: ±2 LSB
• Maximum Settling Time: 13 us
• Settling Time: 10µs
• Number Of Bits: 16
• Data Interface: Parallel
• Number Of Converters: 1
• Voltage Supply Source: Dual ±
• Power Dissipation (max): 625mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Number Of Channels: 1
• Interface Type: Parallel
• Single Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (typ): ±15V
• Power Supply Requirement: Dual
• Single Supply Voltage (min): Not RequiredV
• Single Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): ±13.5V
• Dual Supply Voltage (max): ±16.5V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Package Type: SOIC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. A
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 153 V
(–96 dB). Therefore, the noise floor must remain below this
level in the frequency range of interest. The AD669’s noise
spectral density is shown in Figures 12 and 13. Figure 12 shows
the DAC output noise voltage spectral density for a 20 V span
excluding the reference. This figure shows the l/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/ Hz.
Figure 13 shows the reference noise voltage spectral density.
This figure shows the reference wideband noise to be below
125 nV/ Hz.
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 A current through a 0.5
drop of 153 V, which is 1 LSB at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Figure 12. DAC Output Noise Voltage Spectral Density
Figure 13. Reference Noise Voltage Spectral Density
1000
1000
100
100
10
10
1
1
1
1
10
10
100
100
FREQUENCY – Hz
FREQUENCY – Hz
1k
1k
trace will develop a voltage
10k
10k
100k
100k
1M
1M
10M
10M
–11–
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes should also be utilized, with a single
interconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
One feature that the AD669 incorporates to help the user layout
is the analog pins (V
OFFSET, V
signals from digital signals.
SUPPLY DECOUPLING
The AD669 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes which can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and ground. A 10 F tanta-
lum capacitor in parallel with a 0.1 F ceramic capacitor
provides adequate decoupling. V
to analog ground, while V
ground.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD669, associated analog circuitry and interconnections as
far as possible from logic circuitry. A solid analog ground plane
around the AD669 will isolate large switching ground currents.
For these reasons, the use of wire wrap circuit construction
is not recommended; careful printed circuit construction is
preferred.
GROUNDING
The AD669 has two pins, designated analog ground (AGND)
and digital ground (DGND.) The analog ground pin is the
“high quality” ground reference point for the device. Any exter-
nal loads on the output of the AD669 should be returned to
analog ground. If an external reference is used, this should also
be returned to the analog ground.
If a single AD669 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND keeping lead lengths as short
as possible. Then connect AGND and DGND together at the
AD669. If multiple AD669s are used or the AD669 shares ana-
log supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This single interconnection of grounds prevents large
ground loops and consequently prevents digital currents from
flowing through the analog ground.
OUT
and AGND) are adjacent to help isolate analog
CC
, V
EE
LL
, REF OUT, REF IN, SPAN/BIP
should be decoupled to digital
CC
and V
EE
should be bypassed
AD669