AD669BRZ Analog Devices Inc, AD669BRZ Datasheet - Page 5

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AD669BRZ

Manufacturer Part Number
AD669BRZ
Description
DAC 1-CH R-2R/Current Steering 16-Bit 28-Pin SOIC W
Manufacturer
Analog Devices Inc
Series
DACPORT®r
Datasheet

Specifications of AD669BRZ

Package
28SOIC W
Resolution
16 Bit
Conversion Rate
167 KSPS
Architecture
R-2R|Current Steering
Digital Interface Type
Parallel
Number Of Outputs Per Chip
1
Output Type
Voltage
Signal To Noise Ratio
83(Min) dB
Full Scale Error
±0.1 %FSR
Integral Nonlinearity Error
±2 LSB
Maximum Settling Time
13 us
Settling Time
10µs
Number Of Bits
16
Data Interface
Parallel
Number Of Converters
1
Voltage Supply Source
Dual ±
Power Dissipation (max)
625mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-SOIC (7.5mm Width)
Number Of Channels
1
Interface Type
Parallel
Single Supply Voltage (typ)
Not RequiredV
Dual Supply Voltage (typ)
±15V
Power Supply Requirement
Dual
Single Supply Voltage (min)
Not RequiredV
Single Supply Voltage (max)
Not RequiredV
Dual Supply Voltage (min)
±13.5V
Dual Supply Voltage (max)
±16.5V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
Package Type
SOIC
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AD669BRZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
Part Number:
AD669BRZ-REEL
Manufacturer:
ADI
Quantity:
162
REV. A
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY: Analog Devices defines inte-
gral nonlinearity as the maximum deviation of the actual, ad-
justed DAC output from the ideal analog output (a straight line
drawn from 0 to FS–1 LSB) for any bit combination. This is
also referred to as relative accuracy.
DIFFERENTIAL NONLINEARITY: Differential nonlinearity
is the measure of the change in the analog output, normalized to
full scale, associated with a 1 LSB change in the digital input
code. Monotonic behavior requires that the differential linearity
error be within 1 LSB over the temperature range of interest.
MONOTONICITY: A DAC is monotonic if the output either
increases or remains constant for increasing digital inputs with
the result that the output will always be a single-valued function
of the input.
GAIN ERROR: Gain error is a measure of the output error be-
tween an ideal DAC and the actual device output with all 1s
loaded after offset error has been adjusted out.
OFFSET ERROR: Offset error is a combination of the offset
errors of the voltage-mode DAC and the output amplifier and is
measured with all 0s loaded in the DAC.
BIPOLAR ZERO ERROR: When the AD669 is connected for
bipolar output and 10 . . . 000 is loaded in the DAC, the devia-
tion of the analog output from the ideal midscale value of 0 V is
called the bipolar zero error.
DRIFT: Drift is the change in a parameter (such as gain, offset
and bipolar zero) over a specified temperature range. The drift
temperature coefficient, specified in ppm/ C, is calculated by
measuring the parameter at T
the change in the parameter by the corresponding temperature
change.
TOTAL HARMONIC DISTORTION + NOISE: Total har-
monic distortion + noise (THD+N) is defined as the ratio of the
square root of the sum of the squares of the values of the har-
monics and noise to the value of the fundamental input fre-
quency. It is usually expressed in percent (%).
THD+N is a measure of the magnitude and distribution of lin-
earity error, differential linearity error, quantization error and
noise. The distribution of these errors may be different, depend-
ing upon the amplitude of the output signal. Therefore, to be
the most useful, THD+N should be specified for both large and
small signal amplitudes.
SIGNAL-TO-NOISE RATIO: The signal-to-noise ratio is de-
fined as the ratio of the amplitude of the output when a full-
scale signal is present to the output with no signal present. This
is measured in dB.
DIGITAL-TO-ANALOG GLITCH IMPULSE: This is the
amount of charge injected from the digital inputs to the analog
output when the inputs change state. This is measured at half
scale when the DAC switches around the MSB and as many
as possible switches change state, i.e., from 011 . . . 111 to
100 . . . 000.
DIGITAL FEEDTHROUGH: When the DAC is not selected
(i.e., CS is held high), high frequency logic activity on the digi-
tal inputs is capacitively coupled through the device to show up
as noise on the V
OUT
pin. This noise is digital feedthrough.
MIN
, 25 C and T
MAX
and dividing
–5–
THEORY OF OPERATION
The AD669 uses an array of bipolar current sources with MOS
current steering switches to develop a current proportional to
the applied digital word, ranging from 0 mA to 2 mA. A seg-
mented architecture is used, where the most significant four
data bits are thermometer decoded to drive 15 equal current
sources. The lesser bits are scaled using a R-2R ladder, then ap-
plied together with the segmented sources to the summing node
of the output amplifier. The internal span/bipolar offset resistor
can be connected to the DAC output to provide a 0 V to +10 V
span, or it can be connected to the reference input to provide a
–10 V to +10 V span.
ANALOG CIRCUIT CONNECTIONS
Internal scaling resistors provided in the AD669 may be con-
nected to produce a unipolar output range of 0 V to +10 V or a
bipolar output range of –10 V to +10 V. Gain and offset drift
are minimized in the AD669 because of the thermal tracking of
the scaling resistors with other device components.
UNIPOLAR CONFIGURATION
The configuration shown in Figure 3a will provide a unipolar
0 V to +10 V output range. In this mode, 50
between the span/bipolar offset terminal (Pin 26) and V
25), and between REF OUT (Pin 28) and REF IN (Pin 27). It
is possible to use the AD669 without any external components
by tying Pin 28 directly to Pin 27 and Pin 26 directly to Pin 25.
Eliminating these resistors will increase the gain error by 0.25%
of FSR.
50
R1
LDAC
REF OUT
Figure 3a. 0 V to +10 V Unipolar Voltage Output
REF IN
CS
L1
LDAC
Figure 2. AD669 Functional Block Diagram
CS
L1
23
27
28
6
5
23
27
28
5
6
10k
10k
10V REF
–V
(MSB)
DB15
EE
1
7
10V REF
(MSB)
–V
DB15
16-BIT LATCH
16-BIT LATCH
1
EE
7
16-BIT DAC
+V
16-BIT LATCH
16-BIT LATCH
2
16-BIT DAC
CC
+V
2
CC
AD669
+V
AD669
(LSB)
3
DB0
LL
22
+V
3
(LSB)
LL
DB0
22
4
DGND
10.05k
AMP
10k
4
10.05k
AMP
10k
resistors are tied
26
25
24
AD669
26
24
25
R2
50
SPAN/
BIP OFF
AGND
V
OUT
GND
OUT
OUTPUT
(Pin

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