MT48LC2M32B2TG-7 IT:G TR Micron Technology Inc, MT48LC2M32B2TG-7 IT:G TR Datasheet - Page 27
![DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R](/photos/7/22/72264/557-86-tsop_sml.jpg)
MT48LC2M32B2TG-7 IT:G TR
Manufacturer Part Number
MT48LC2M32B2TG-7 IT:G TR
Description
DRAM Chip SDRAM 64M-Bit 2Mx32 3.3V 86-Pin TSOP-II T/R
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48LC2M32B2P-6G_TR.pdf
(69 pages)
Specifications of MT48LC2M32B2TG-7 IT:G TR
Package
86TSOP-II
Density
64 Mb
Address Bus Width
13 Bit
Operating Supply Voltage
3.3 V
Maximum Clock Rate
143 MHz
Maximum Random Access Time
17|8|5.5 ns
Operating Temperature
-40 to 85 °C
Format - Memory
RAM
Memory Type
SDRAM
Memory Size
64M (2Mx32)
Speed
143MHz
Interface
Parallel
Voltage - Supply
3 V ~ 3.6 V
Package / Case
86-TSOP
Organization
2Mx32
Address Bus
13b
Access Time (max)
17/8/5.5ns
Operating Supply Voltage (typ)
3.3V
Package Type
TSOP-II
Operating Temp Range
-40C to 85C
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
3V
Supply Current
160mA
Pin Count
86
Mounting
Surface Mount
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
557-1075-2
Figure 14:
PDF: 09005aef811ce1fe/Source: 09005aef811ce1d5
64MSDRAMx32_2.fm - Rev. J 12/08 EN
READ-to-PRECHARGE
Note:
COMMAND
COMMAND
COMMAND
ADDRESS
ADDRESS
ADDRESS
DQM is LOW.
CLK
CLK
CLK
DQ
DQ
DQ
BANK a,
BANK a,
BANK a,
COL n
COL n
COL n
T0
T0
T0
READ
READ
READ
CL = 1
CL = 2
T1
T1
T1
NOP
NOP
NOP
D
OUT
CL = 3
n
27
T2
T2
T2
NOP
NOP
NOP
D
D
n + 1
OUT
OUT
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
T3
NOP
NOP
NOP
D
n + 2
D
D
n + 1
OUT
OUT
OUT
n
PRECHARGE
PRECHARGE
PRECHARGE
(a or all)
(a or all)
(a or all)
BANK
BANK
BANK
T4
T4
T4
X = 0 cycles
X = 1 cycle
D
n + 3
D
n + 2
D
n + 1
OUT
OUT
OUT
X = 2 cycles
T5
T5
T5
NOP
NOP
NOP
D
n + 3
D
n + 2
OUT
OUT
t RP
t RP
t RP
©2001 Micron Technology, Inc. All rights reserved.
64Mb: x32 SDRAM
T6
T6
T6
NOP
NOP
NOP
D
n + 3
OUT
DON’T CARE
Commands
BANK a,
BANK a,
BANK a,
ACTIVE
ACTIVE
ACTIVE
T7
T7
T7
ROW
ROW
ROW