723643L15PF Integrated Device Technology (Idt), 723643L15PF Datasheet - Page 14

• Manufacturer Part Number: 723643L15PF
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723643L15PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 36 Kb
• Organization: 1Kx36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-B35. For
an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. (In this case,
B18-B35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on B0-B8. (In this case, B9-B35 are indeterminate.)
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH.
an 18-bit bus size, 18 bits of mailbox data are placed on A0-A17. (In this case,
A18-A35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are
placed on A0-A8. (In this case, A9-A35 are indeterminate.)
when new data is written to the register. The Endian Select feature has no effect
on mailbox data. For mail register and mail register flag timing diagrams, see
Figure 17 and 18.
BUS SIZING
9-bit byte format for data read from the FIFO. The levels applied to the Port B
Bus Size Select (SIZE) and the Bus-Match Select (BM) determine the Port B
bus size. These levels should be static throughout FIFO operation. Both bus
size selections are implemented at the completion of Reset, by the time the Full/
Input Ready flag is set HIGH, as shown in Figure 2.
B when the bus size selection is either byte-or word-size. They are referred
to as Big-Endian (most significant byte first) and Little-Endian (least significant
byte first). The level applied to the Big-Endian Select (BE) input during the LOW-
IDT723623/723633/723643 BUS-MATCHING SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition
For a 36-bit bus size, 36 bits of mailbox data are placed on A0-A35. For
The data in a mail register remains intact after it is read and changes only
The Port B bus can be configured in a 36-bit long word, 18-bit word, or
Two different methods for sequencing data transfer are available for Port
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to-HIGH transition of RS1 selects the endian method that will be active during
FIFO operation. BE is a don’t care input when the bus size selected for Port B
is long word. The endian method is implemented at the completion of Reset, by
the time the Full/Input Ready flag is set HIGH, as shown in Figure 2.
on the IDT723623/723633/723643. Bus-matching operations are done after
data is read from the FIFO RAM. These bus-matching operations are not
available when transferring data via mailbox registers. Furthermore, both the
word- and byte-size bus selections limit the width of the data bus that can be used
for mail register operations. In this case, only those byte lanes belonging to the
selected word- or byte-size bus can carry mailbox data. The remaining data
outputs will be indeterminate. The remaining data inputs will be don’t care inputs.
For example, when a word-size bus is selected, then mailbox data can be
transmitted only between A0-A17 and B0-B17. When a byte-size bus is
selected, then mailbox data can be transmitted only between A0-A8 and B0-
B8. (See Figures 17 and 18).
BUS-MATCHING FIFO READS
word bus size is implemented, the entire long word immediately shifts to the FIFO
output register. If byte or word size is implemented on Port B, only the first one
or two bytes appear on the selected portion of the FIFO output register, with the
rest of the long word stored in auxiliary registers. In this case, subsequent FIFO
reads output the rest of the long word to the FIFO output register in the order
shown by Figure 2.
outputs are indeterminate.
Data is read from the FIFO RAM in 36-bit long word increments. If a long
When reading data from FIFO in byte or word format, the unused B0-B35
Only 36-bit long word data is written to or read from the FIFO memory
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