723643L15PF Integrated Device Technology (Idt), 723643L15PF Datasheet - Page 2

• Manufacturer Part Number: 723643L15PF
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723643L15PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 36 Kb
• Organization: 1Kx36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

DESCRIPTION (CONTINUED)
clock frequencies up to 83 MHz and have read access times as fast as 8 ns.
The 256/512/1,024 x 36 dual-port SRAM FIFO buffers data from port A to port
B. FIFO data on Port B can output in 36-bit, 18-bit, or 9-bit formats with a choice
of Big- or Little-Endian configurations.
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
PIN CONFIGURATION
IDT723623/723633/723643 BUS-MATCHING SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
These devices are synchronous (clocked) FIFOs, meaning each port
BE/FWFT
INDEX
W/RA
CLKA
GND
GND
GND
GND
GND
ENA
A35
A34
A33
A32
A30
A28
A27
A26
A25
A21
A19
A17
A31
A29
A24
A23
A22
A20
A18
A16
A15
A14
A13
A12
A11
A10
Vcc
Vcc
Vcc
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
TQFP (PK128-1, order code: PF)
TOP VIEW
2
registers. The mailbox registers' width matches the selected Port B bus width.
Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail
has been stored.
Reset initializes the read and write pointers to the first location of the memory
array and selects serial flag programming, parallel flag programming, or one
of three possible default flag offset settings, 8, 16 or 64.
memory. Unlike Reset, any settings existing prior to Partial Reset (i.e.,
programming method and partial flag default offsets) are retained. Partial Reset
Communication between each port may bypass the FIFO via two mailbox
Two kinds of reset are available on these FIFOs: Reset and Partial Reset.
Partial Reset also sets the read and write pointers to the first location of the
COMMERCIAL TEMPERATURE RANGE
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
3269 drw02
CLKB
Vcc
Vcc
B35
B34
B33
B32
GND
GND
B31
B30
B29
B28
B27
B26
Vcc
B25
B24
BM
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
SIZE
Vcc
B15
B14
B13
B12
GND
B11
B10