723643L15PF Integrated Device Technology (Idt), 723643L15PF Datasheet - Page 4

• Manufacturer Part Number: 723643L15PF
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 128-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 723643L15PF

• Package: 128TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 36 Kb
• Organization: 1Kx36
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

PIN DESCRIPTIONS
IDT723623/723633/723643 BUS-MATCHING SyncFIFO™
256 x 36, 512 x 36, 1,024 x 36
A0-A35
AE
AF
B0-B35
BE/FWFT
BM
CLKA
CLKB
CSA
CSB
EF/OR
ENA
ENB
FF/IR
FS1/SEN
FS0/SD
MBA
MBB
MBF1
Symbol
(1)
Port A Data
Almost-Empty
Flag (Port B)
Almost-Full
Flag (Port A)
Port B Data
Big-Endian/
First Word
Fall Through
Bus-Match
Select (Port B)
Port A Clock
Port B Clock
Port A Chip
Select
Port B Chip
Select
Empty/Output
Ready Flag
(Port B)
Port A Enable
Port B Enable
Full/Input
Ready Flag
(Port A)
Flag Offset
Select 1/
Serial Enable,
Flag Offset
Select 0/
Serial Data
Port A Mailbox
Select
Port B Mailbox
Select
Mail1 Register
Flag
Name
I/O
I/O
O
O
O
O
I/O
O
I
I
I
I
I
I
I
I
I
I
I
I
36-bit bidirectional data port for side A.
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in the FIFO
is less than or equal to the value in the Almost-Empty B offset register, X.
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in the
FIFO is less than or equal to the value in the Almost-Full A offset register, Y.
36-bit bidirectional data port for side B.
This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case,
depending on the bus size, the most significant byte or word written to Port A is read from Port B first. A
LOW on BE will select Little-Endian operation. In this case, the least significant byte or word written to Port A
is read from Port B first. After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT
Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the
level on FWFT must be static throughout device operation.
A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A
LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian
arrangement for Port B. The level of BM must be static throughout device operation.
CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or
coincident to CLKB. FF/IR and AF are synchronized to the LOW-to-HIGH transition of CLKA.
CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or
coincident to CLKA. EF/OR and AE are synchronized to the LOW-to-HIGH transition of CLKB.
CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write on Port B. The B0-B35
outputs are in the high-impedance state when CSB is HIGH.
This is a dual function pin. In the IDT Standard mode, the EF function is selected. EF indicates whether or
not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates the presence of valid
data on the B0-B35 outputs, available for reading. EF/OR is synchronized to the LOW-to-HIGH transition of CLKB.
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B.
This is a dual function pin. In the IDT Standard mode, the FF function is selected. FF indicates whether or
not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there
is space available for writing to the FIFO memory. FF/IR is synchronized to the LOW-to-HIGH transition of
CLKA.
FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Reset,
FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register
load from Port A, and serial load.
When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous
to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present
for the IDT723623, 18 for the IDT723633, and 20 for the IDT723643. The first bit write stores the Y-register
MSB and the last bit write stores the X-register LSB.
A HIGH level on MBA chooses a mailbox register for a Port A read or write operation.
A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-B35
outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level
selects FIFO data for output.
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to
the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB
when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Reset (RS1) or Partial
Reset (PRS).
programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel
on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 16
4
Description
COMMERCIAL TEMPERATURE RANGE