N25Q128A13B1240E NUMONYX, N25Q128A13B1240E Datasheet - Page 26
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N25Q128A13B1240E
Manufacturer Part Number
N25Q128A13B1240E
Description
SERIAL NOR, 128MB
Manufacturer
NUMONYX
Datasheet
1.N25Q128A13BSF40G.pdf
(180 pages)
- Current page: 26 of 180
- Download datasheet (6Mb)
Operating features
N25Q128 - 3 V
the reset mode and a time of tRHSL is then required before the device can be reselected by
driving Chip Select (S) Low. For the value of tRHSL, see
Table 32.: AC
Characteristics. All
the lock bits are reset to 0 after a Reset Low pulse.
The Hold/Reset feature is not available when the Hold (Reset) / DQ3 pin is used as I/O
(DQ3 functionality) during Quad Instructions: QOFR, QIOFR,QIFP and QIEFP.
The Hold/Reset feature can be disabled by using of the bit 4 of the VECR.
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