LCMXO256C-3TN100I LATTICE SEMICONDUCTOR, LCMXO256C-3TN100I Datasheet - Page 26

• Manufacturer Part Number: LCMXO256C-3TN100I
• Description: CPLD MachXO Family 128 Macro Cells 1.8V/2.5V/3.3V 100-Pin TQFP Tray
• Manufacturer: LATTICE SEMICONDUCTOR

Specifications of LCMXO256C-3TN100I

• Package: 100TQFP
• Family Name: MachXO
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 4.9 ns
• Number Of User I/os: 78
• Typical Operating Supply Voltage: 1.8|2.5|3.3 V
• Memory Type: SRAM
• Operating Temperature: -40 to 100 °C

Lattice Semiconductor
Figure 2-22. MachXO Configuration and Programming
Density Shifting
The MachXO family has been designed to enable density migration in the same package. Furthermore, the archi-
tecture ensures a high success rate when performing design migration from lower density parts to higher density
parts. In many cases, it is also possible to shift a lower utilization design targeted for a high-density device to a
lower density device. However, the exact details of the final resource utilization will impact the likely success in
each case.
Port
Mode
Program in seconds
Memory Space
Non-Volatile
Background
ISP 1149.1 TAP Port
microseconds
Download in
Power-up
Refresh
2-23
SRAM Memory
Space
1532
MachXO Family Data Sheet
Configure in milliseconds
Architecture