XC2C64A-7CPG56I Xilinx Inc, XC2C64A-7CPG56I Datasheet - Page 8

• Manufacturer Part Number: XC2C64A-7CPG56I
• Description: CPLD CoolRunner™-II Family 1.5K Gates 64 Macro Cells 159MHz 0.18um (CMOS) Technology 1.8V 56-Pin CSBGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7CPG56I

• Package: 56CSBGA
• Family Name: CoolRunner™-II
• Device System Gates: 1500
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 7.5 ns
• Number Of User I/os: 45
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 1.8 V
• Maximum Operating Frequency: 159 MHz
• Number Of Product Terms Per Macro: 40
• Operating Temperature: -40 to 85 °C
• Features: Programmable
• Package / Case: 56-CSBGA
• Mounting Type: Surface Mount
• Voltage: 1.8V
• Number Of I /o: 45
• Memory Type: CMOS
• Programmable Type: In System Programmable
• Number Of Macrocells: 64
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Gates: 1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

XC2C64A CoolRunner-II CPLD
Internal Timing Parameters (Continued)
8
1.
I/O Standard Time Adder Delays 2.5V CMOS
T
T
T
T
I/O Standard Time Adder Delays 3.3V CMOS/TTL
T
T
T
T
OUT25
OUT33
IN25
HYS25
SLEW25
IN33
HYS33
SLEW33
1.5 ns input pin signal rise/fall.
Symbol
Standard input adder
Hysteresis input adder
Output adder
Output slew rate adder
Standard input adder
Hysteresis input adder
Output adder
Output slew rate adder
Parameter
(1)
www.xilinx.com
Min.
-
-
-
-
-
-
-
-
-5
Max.
0.5
2.5
0.8
4.0
0.5
2.0
1.2
4.0
Min.
DS311 (v2.3) November 19, 2008
-
-
-
-
-
-
-
-
-7
Product Specification
Max.
0.6
3.0
0.9
5.0
0.6
3.0
1.4
5.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
R