XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 178

• Manufacturer Part Number: XC3S500E-4PQG208C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4PQG208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1520

Pinout Descriptions
Footprint Migration Differences
Table 136
ences between the XC3S100E, the XC3S250E, and the
XC3S500E FPGAs that may affect easy migration between
devices in the CP132 package. There are 14 such balls. All
other pins not listed in
between Spartan-3E devices available in the CP132 pack-
age.
The XC3S100E is duplicated on both the left and right sides
of the table to show migrations to and from the XC3S250E
and the XC3S500E. The arrows indicate the direction for
easy migration. A double-ended arrow (
Table 136: CP132 Footprint Migration Differences
178
CP132
DIFFERENCES
M10
Ball
C11
N10
A12
B11
B12
P11
M9
B4
C4
D1
D2
K3
N9
Legend:
summarizes any footprint and functionality differ-
This pin is identical on the device on the left and the right.
This pin can unconditionally migrate from the device on the left to the device on the right. Migration in the other direction may be possible
depending on how the pin is configured for the device on the right.
This pin can unconditionally migrate from the device on the right to the device on the left. Migration in the other direction may be possible
depending on how the pin is configured for the device on the left.
Bank
0
0
0
0
0
0
3
3
3
2
2
2
2
2
N.C.
INPUT
N.C.
N.C.
N.C.
INPUT
N.C.
I/O
VREF(INPUT)
N.C.
N.C.
N.C.
N.C.
VREF(INPUT)
XC3S100E
Type
Table 136
unconditionally migrate
Migration
14
) indicates that
XC3S250E
VREF(I/O)
VREF(I/O)
I/O (Diff)
DUAL
DUAL
DUAL
DUAL
Type
www.xilinx.com
I/O
I/O
I/O
I/O
I/O
I/O
I/O
the two pins have identical functionality. A left-facing arrow
( ) indicates that the pin on the device on the right uncon-
ditionally migrates to the pin on the device on the left. It may
be possible to migrate the opposite direction depending on
the I/O configuration. For example, an I/O pin (Type = I/O)
can migrate to an input-only pin (Type = INPUT) if the I/O
pin is configured as an input.
The XC3S100E FPGA in the CP132 package has four fewer
BPI-mode address lines than the XC3S250E and
XC3S500E.
Migration
0
XC3S500E
VREF(I/O)
VREF(I/O)
I/O (Diff)
DUAL
DUAL
DUAL
DUAL
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Migration
DS312-4 (v3.8) August 26, 2009
14
Product Specification
N.C.
INPUT
N.C.
N.C.
N.C.
INPUT
N.C.
I/O
VREF(INPUT)
N.C.
N.C.
N.C.
N.C.
VREF(INPUT)
XC3S100E
Type
R