XC3S500E-4PQG208C Xilinx Inc, XC3S500E-4PQG208C Datasheet - Page 96

• Manufacturer Part Number: XC3S500E-4PQG208C
• Description: FPGA Spartan®-3E Family 500K Gates 10476 Cells 572MHz 90nm (CMOS) Technology 1.2V 208-Pin PQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3Er

Specifications of XC3S500E-4PQG208C

• Package: 208PQFP
• Family Name: Spartan®-3E
• Device Logic Cells: 10476
• Device Logic Units: 1164
• Device System Gates: 500000
• Number Of Registers: 9312
• Maximum Internal Frequency: 572 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 158
• Ram Bits: 368640
• Number Of Logic Elements/cells: 10476
• Number Of Labs/clbs: 1164
• Total Ram Bits: 368640
• Number Of I /o: 158
• Number Of Gates: 500000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 122-1520

Functional Description
can also be eliminated from the interface. However,
RDWR_B must remain Low during configuration.
After configuration, all of the interface pins except DONE
and PROG_B are available as user I/Os. Alternatively, the
bidirectional SelectMAP configuration interface is available
after configuration. To continue using SelectMAP mode, set
the Persist bitstream generator option to Yes. The external
host can then read and verify configuration data.
Table 65: Slave Parallel Mode Connections
96
HSWAP
M[2:0]
D[7:0]
BUSY
CSI_B
RDWR_B
CCLK
CSO_B
Pin Name
FPGA Direction
Output
Output
Input
Input
Input
Input
Input
Input
User I/O Pull-Up Control. When
Low during configuration, enables
pull-up resistors in all I/O pins to
respective I/O bank V
0: Pull-ups during configuration
1: No pull-ups
Mode Select. Selects the FPGA
configuration mode. See
Considerations for the HSWAP,
M[2:0], and VS[2:0]
Data Input.
Busy Indicator.
Chip Select Input. Active Low.
Read/Write Control. Active Low
write enable.
Configuration Clock. If CCLK PCB
trace is long or has multiple
connections, terminate this output to
maintain signal integrity. See
Design
Chip Select Output. Active Low.
Considerations.
Description
Pins.
CCO
www.xilinx.com
Design
input.
CCLK
The Persist option will maintain A20-A23 as configuration
pins although they are not used in SelectMAP mode.
The Slave Parallel mode is also used with BPI mode to cre-
ate multi-FPGA daisy-chains. The lead FPGA is set for BPI
mode configuration; all the downstream daisy-chain FPGAs
are set for Slave Parallel configuration, as highlighted in
Figure
Drive at valid logic level
throughout configuration.
M2 = 1, M1 = 1, M0 = 0 Sampled
when INIT_B goes High.
Byte-wide data provided by host.
FPGA captures data on rising
CCLK edge.
If CCLK frequency is < 50 MHz,
this pin may be ignored. When
High, indicates that the FPGA is
not ready to receive additional
configuration data. Host must
hold data an additional clock
cycle.
Must be Low throughout
configuration.
Must be Low throughout
configuration.
External clock.
Not used in single FPGA
applications. In a daisy-chain
configuration, this pin connects to
the CSI_B pin of the next FPGA in
the chain. Actively drives.
59.
During Configuration
DS312-2 (v3.8) August 26, 2009
User I/O
User I/O
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O. If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O If bitstream
option Persist=Yes,
becomes part of
SelectMap parallel
peripheral interface.
User I/O
After Configuration
Product Specification
R