XC5VLX220-1FF1760I Xilinx Inc, XC5VLX220-1FF1760I Datasheet - Page 191

• Manufacturer Part Number: XC5VLX220-1FF1760I
• Description: FPGA Virtex®-5 Family 221184 Cells 65nm (CMOS) Technology 1V 1760-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 LXr

Specifications of XC5VLX220-1FF1760I

• Package: 1760FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 221184
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 800
• Ram Bits: 7077888
• Number Of Logic Elements/cells: 221184
• Number Of Labs/clbs: 17280
• Total Ram Bits: 7077888
• Number Of I /o: 800
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1760-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1760-500-G - BOARD DEV VIRTEX 5 FF1760
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
or flip-flop is available to implement a synchronous read. In this case, the clock-to-out of
the flip-flop determines the overall delay and improves performance. However, one
additional cycle of clock latency is added. Any of the 32 bits can be read out
asynchronously (at the O6 LUT outputs) by varying the 5-bit address. This capability is
useful in creating smaller shift registers (less than 32 bits). For example, when building a
13-bit shift register, simply set the address to the 13
diagram of a 32-bit shift register.
X-Ref Target - Figure 5-15
Figure 5-16
generator.
X-Ref Target - Figure 5-16
SHIFTIN (D)
Address (A[4:0])
illustrates an example shift register configuration occupying one function
SHIFTIN (D)
SHIFTIN (MC31 of Previous LUT)
A[4:0]
CLK
CE
CLK
WE
Figure 5-15: 32-bit Shift Register Configuration
Figure 5-16: Representation of a Shift Register
(AX)
www.xilinx.com
5
(WE/CE)
(A[6:2])
(CLK)
5
32-bit Shift Register
DI1
A[6:2]
CLK
CE
SRLC32E
MUX
Q
SRL32
MC31
O6
th
bit.
Figure 5-15
SHIFTOUT (Q31)
D Q
SHIFTOUT(Q31)
(AQ)
UG190_5_16_050506
(Optional)
is a logic block
ug190_5_15_050506
Output (Q)
Registered
Output
CLB Overview
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