XC5VSX50T-1FFG665I Xilinx Inc, XC5VSX50T-1FFG665I Datasheet - Page 13

FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA

XC5VSX50T-1FFG665I

Manufacturer Part Number
XC5VSX50T-1FFG665I
Description
FPGA Virtex®-5 Family 52224 Cells 65nm (CMOS) Technology 1V 665-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665I

Package
665FCBGA
Family Name
Virtex®-5
Device Logic Units
52224
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
360
Ram Bits
4866048
Number Of Logic Elements/cells
52224
Number Of Labs/clbs
4080
Total Ram Bits
4866048
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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GTP_DUAL Tile Specifications
GTP_DUAL Tile DC Characteristics
Table 24: Absolute Maximum Ratings for GTP_DUAL Tiles
Table 25: Recommended Operating Conditions for GTP_DUAL Tiles
Table 26: DC Characteristics Over Recommended Operating Conditions for GTP_DUAL Tiles
DS202 (v5.3) May 5, 2010
Product Specification
Notes:
1.
Notes:
1.
2.
Notes:
1.
2.
3.
MGTAVTTRXC
MGTAVCCPLL
MGTAVTTRX
MGTAVTTTX
MGTAVTTRXC
MGTAVCCPLL
I
I
MGTAVTTRX
MGTAVCC
MGTAVTTRXC
MGTAVTTTX
I
MGTAVCCPLL
I
MGTR
MGTAVTTTX
MGTAVTTRX
I
MGTAVCC
Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied.
Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Each voltage listed requires the filter circuit described in UG196: Virtex-5 FPGA RocketIO GTP Transceiver User Guide.
Voltages are specified for the temperature range of T
Symbol
Typical values are specified at nominal voltage, 25°C, with a 3.2 Gb/s line rate.
ICC numbers are given per GTP_DUAL tile with both GTP transceivers operating with default settings.
AC coupled TX/RX link.
MGTAVCC
Symbol
Symbol
REF
(1)
(1)
(1)
(1)
(1)
GTP_DUAL tile transmitter termination supply current
GTP_DUAL tile shared PLL supply current
GTP_DUAL tile resistor termination calibration supply current
GTP_DUAL tile receiver termination supply current
GTP_DUAL tile internal analog supply current
Precision reference resistor for internal calibration termination
Analog supply voltage for the GTP_DUAL shared PLL relative to GND
Analog supply voltage for the GTP_DUAL transmitters relative to GND
Analog supply voltage for the GTP_DUAL receivers relative to GND
Analog supply voltage for the GTP_DUAL common circuits relative to GND
Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
Analog supply voltage for the GTP_DUAL shared PLL relative to GND
Analog supply voltage for the GTP_DUAL transmitters relative to GND
Analog supply voltage for the GTP_DUAL receivers relative to GND
Analog supply voltage for the GTP_DUAL common circuits relative to GND
Analog supply voltage for the resistor calibration circuit of the GTP_DUAL
column
Description
Description
Description
J
= –40°C to +100°C.
www.xilinx.com
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
(3)
(2)
(1)(2)
Min
49.9 ± 1% tolerance
1.14
1.14
1.14
0.95
1.14
Min
–0.5 to 1.32
–0.5 to 1.32
–0.5 to 1.32
–0.5 to 1.32
–0.5 to 1.1
Typ
0.1
0.1
36
56
71
(1)
Max
110
0.5
0.5
60
90
Max
1.26
1.26
1.26
1.05
1.26
Units
Units
mA
mA
mA
mA
mA
Units
Ω
V
V
V
V
V
V
V
V
V
V
13

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