XC5VSX95T-1FF1136I Xilinx Inc, XC5VSX95T-1FF1136I Datasheet - Page 104
XC5VSX95T-1FF1136I
Manufacturer Part Number
XC5VSX95T-1FF1136I
Description
FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-1FF1136I
Package
1136FCBGA
Family Name
Virtex®-5
Device Logic Units
94208
Typical Operating Supply Voltage
1 V
Maximum Number Of User I/os
640
Ram Bits
8994816
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With
HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
Number Of Gates
-
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VSX95T-1FF1136I
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 3: Phase-Locked Loops (PLLs)
Reference Clock Switching
104
X-Ref Target - Figure 3-8
All “O” counters are equivalent, anything O0 can do, O1 can do. The PLL outputs are
flexible when connecting to the global clock network since they are identical. In most cases,
this level of detail is imperceptible to the designer as the software and PLL Wizard
determines the proper settings through the PLL attributes and Wizard inputs.
The PLL reference clock can be dynamically switched by using the CLKINSEL pin. The
switching is done asynchronously. Since the clock signal can generate a narrow pulse
resulting in erroneous behavior of the PLL, the PLL should be held in RESET while
selecting the alternate clock with the CLKINSEL (CLKSRC) signal. The PLL clock mux
switching is shown in
mux. No synchronization logic is present.
X-Ref Target - Figure 3-9
8 Phases
Counter
Outputs
VCO
135°
180°
225°
270°
315°
45°
90°
O0
O1
O2
O3
0°
One Cycle Delay
Figure
CLKSRC
CLKIN1
CLKIN2
www.xilinx.com
IBUFG
IBUFG
Figure 3-8: Selecting VCO Phases
BUFG
BUFG
Figure 3-9: Input Clock Switching
DCM
DCM
3-9. The CLKINSEL (CLKSRC) signal directly controls the
ug190_3_09_050906
PLL
CLKIN
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_03_08_032506
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