XC5VSX95T-1FF1136I Xilinx Inc, XC5VSX95T-1FF1136I Datasheet - Page 43

• Manufacturer Part Number: XC5VSX95T-1FF1136I
• Description: FPGA Virtex®-5 Family 94208 Cells 65nm (CMOS) Technology 1V 1136-Pin FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX95T-1FF1136I

• Package: 1136FCBGA
• Family Name: Virtex®-5
• Device Logic Units: 94208
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 640
• Ram Bits: 8994816
• Number Of Logic Elements/cells: 94208
• Number Of Labs/clbs: 7360
• Total Ram Bits: 8994816
• Number Of I /o: 640
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1136-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: HW-AFX-FF1136-500-G - BOARD DEV VIRTEX 5 FF1136
• Number Of Gates: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
BUFR Primitive
the global clock tree. Each BUFR can drive the four regional clock nets in the region it is
located, and the four clock nets in the adjacent clock regions (up to three clock regions).
Unlike BUFIOs, BUFRs can drive the I/O logic and logic resources (CLB, block RAM, etc.)
in the existing and adjacent clock regions. BUFRs can be driven by clock capable pins or
local interconnect. In addition, BUFR is capable of generating divided clock outputs with
respect to the clock input. The divide values are an integer between one and eight. BUFRs
are ideal for source-synchronous applications requiring clock domain crossing or serial-to-
parallel conversion. There are two BUFRs in a typical clock region (four regional clock
networks). The center column does not have BUFRs.
BUFR is a clock-in/clock-out buffer with the capability to divide the input clock frequency.
X-Ref Target - Figure 1-20
Table 1-7: BUFR Port List and Definitions
Additional Notes on the CE Pin
When CE is asserted/deasserted, the output clock signal turns on/off. When global
set/reset (GSR) signal is High, BUFR does not toggle, even if CE is held High. The BUFR
output toggles after the GSR signal is deasserted when a clock is on the BUFR input port.
O
CE
CLR
I
Port Name
Output
Input
Input
Input
Type
www.xilinx.com
CLR
Figure 1-20: BUFR Primitive
CE
I
1
1
1
1
Width
ug190_1_20_032306
Clock output port
Clock enable port. Cannot be used in
BYPASS mode.
Asynchronous clear for the divide
logic, and sets the output Low. Cannot
be used in BYPASS mode.
Clock input port
O
Regional Clocking Resources
Definition
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