XC6VCX75T-2FF484C Xilinx Inc, XC6VCX75T-2FF484C Datasheet - Page 49

• Manufacturer Part Number: XC6VCX75T-2FF484C
• Description: FPGA Virtex®-6 CXT Family 74496 Cells 40nm (CMOS) Technology 1V 484-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC6VCX75T-2FF484C

• Package: 484FCBGA
• Family Name: Virtex®-6 CXT
• Device Logic Units: 74496
• Number Of Registers: 93120
• Typical Operating Supply Voltage: 1 V
• Maximum Number Of User I/os: 240
• Ram Bits: 5750784

Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 CXT FPGA clock
transmitter and receiver data-valid windows.
Table 64: Duty Cycle Distortion and Clock-Tree Skew
Table 65: Package Skew
DS153 (v1.6) February 11, 2011
Product Specification
Notes:
1.
2.
Notes:
1.
2.
T
T
T
T
T
T
T
DCD_CLK
CKSKEW
DCD_BUFIO
BUFIOSKEW
BUFIOSKEW2
DCD_BUFR
PKGSKEW
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
The T
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
These values represent the worst-case skew between any two SelectIO resources in the package: shortest flight time to longest flight time
from Pad to Ball (7.0 ps per mm).
Package trace length information is available for these device/package combinations. This information can be used to deskew the package.
Symbol
Symbol
CKSKEW
value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
Global Clock Tree Duty Cycle Distortion
Global Clock Tree Skew
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock region
I/O clock tree skew across three clock regions
Regional clock tree duty cycle distortion
Package Skew
Description
Description
(1)
(2)
www.xilinx.com
(1)
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Device
XC6VCX75T
XC6VCX130T
XC6VCX195T
XC6VCX240T
Device
All
All
All
All
All
Package
FF1156
FF1156
FF1156
FF484
FF784
FF484
FF784
FF784
FF784
Virtex-6 CXT Family Data Sheet
0.08
0.12
0.18
0.29
0.31
0.31
0.03
0.22
0.15
-2
Speed Grade
Value
146
165
146
182
95
0.12
0.18
0.29
0.31
0.31
0.08
0.03
0.22
0.15
-1
Units
Units
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
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