XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 103
![no-image](/images/no-image-200.jpg)
XCV100E-6FG256I
Manufacturer Part Number
XCV100E-6FG256I
Description
FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Specifications of XCV100E-6FG256I
Package
256FBGA
Family Name
VirtexÂ-E
Device Logic Gates
32400
Device Logic Units
2700
Device System Gates
128236
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
176
Ram Bits
81920
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
81920
Number Of I /o
176
Number Of Gates
128236
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Table 9: HQ240 Differential Pin Pair Summary
XCV600E, XCV1000E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Pair
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Note 1: AO in the XCV600E.
Bank
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
R
P56
P52
P49
P46
P41
P38
P35
P33
P27
P23
P20
P17
P12
Pin
P9
P6
P4
P
P57
P53
P50
P47
P42
P39
P36
P34
P28
P24
P21
P18
P13
P10
Pin
P7
P5
N
AO
√
√
√
√
√
√
√
1
√
√
√
√
√
√
√
1
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
BG352 Ball Grid Array Packages
XCV100E, XCV200E, and XCV300E devices in BG352 Ball
Grid Array packages have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V
ately following
information.
Table 10: BG352 — XCV100E, XCV200E, XCV300E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Virtex™-E 1.8 V Field Programmable Gate Arrays
REF
Table
, it can be used as general I/O. Immedi-
IO_VREF_0_L0N_YY
IO_VREF_0_L2N_YY
IO_VREF_0_L4N_YY
IO_VREF_0_L8N_Y
Pin Description
10, see
IO_L0P_YY
IO_L1N_YY
IO_L1P_YY
IO_L2P_YY
IO_L4P_YY
IO_L5N_YY
IO_L5P_YY
IO_L7N_Y
IO_L7P_Y
IO_L8P_Y
IO_L3N
IO_L6N
IO_L3P
IO_L6P
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Table 11
for Differential Pair
Module 4 of 4
Pin #
C23
D21
C20
D16
B24
A24
B21
B18
D22
C22
B23
A23
D20
C21
B22
B20
A21
D18
C19
B19
D17
C18
C17
A18
B17
C16
A16
D15
1
1
2
1
1
1
1
1
17
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