XCV100E-6FG256I Xilinx Inc, XCV100E-6FG256I Datasheet - Page 48

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XCV100E-6FG256I

Manufacturer Part Number
XCV100E-6FG256I
Description
FPGA Virtex™-E Family 32.4K Gates 2700 Cells 357MHz 0.18um (CMOS) Technology 1.8V 256-Pin FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-Er
Datasheets

Specifications of XCV100E-6FG256I

Package
256FBGA
Family Name
Virtex™-E
Device Logic Gates
32400
Device Logic Units
2700
Device System Gates
128236
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
176
Ram Bits
81920
Number Of Logic Elements/cells
2700
Number Of Labs/clbs
600
Total Ram Bits
81920
Number Of I /o
176
Number Of Gates
128236
Voltage - Supply
1.71 V ~ 1.89 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XCV100E-6FG256I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XCV100E-6FG256I
Manufacturer:
XILINX
0
Virtex™-E 1.8 V Field Programmable Gate Arrays
HSTL
A sample circuit illustrating a valid termination technique for
HSTL_I appears in
valid termination technique for HSTL_III appears in
Figure
Table 25: HSTL Class I Voltage Specification
Table 26: HSTL Class III Voltage Specification
Module 2 of 4
42
V
V
V
V
V
V
V
I
I
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
OH
OL
OH
OL
CCO
REF
TT
IH
IL
CCO
REF
TT
IH
IL
Parameter
at V
Parameter
at V
Note: Per EIA/JESD8-6, “The value of V
by the user to provide optimum noise margin in the use
conditions specified by the user.”
at V
at V
(1)
47.
OL
OL
OH
OH
Figure 46: Terminated HSTL Class I
(mA)
(mA)
(mA)
(mA)
V
HSTL Class I
CCO
= 1.5V
Figure
V
V
V
V
REF
CCO
REF
CCO
1.40
0.68
Min
−8
V
1.40
8
Min
-
-
REF
−8
24
+ 0.1
– 0.4
-
-
-
-
46. A sample circuit illustrating a
+ 0.1
– 0.4
= 0.75V
Z = 50
50Ω
V
TT
V
CCO
= 0.75V
1.50
0.75
Typ
V
1.50
0.90
x133_10_111699
Typ
-
-
-
-
-
CCO
× 0.5
-
-
-
-
-
-
REF
is to be selected
V
V
REF
REF
Max
1.60
Max
1.60
0.90
0.4
0.4
-
-
-
-
-
-
-
-
-
-
-
– 0.1
– 0.1
www.xilinx.com
A sample circuit illustrating a valid termination technique for
HSTL_IV appears in
Table 27: HSTL Class IV Voltage Specification
V
V
V
V
V
V
V
I
I
OH
OL
OH
OL
CCO
REF
TT
IH
IL
Parameter
at V
Note: Per EIA/JESD8-6, “The value of V
by the user to provide optimum noise margin in the use
conditions specified by the user.
at V
OL
OH
Figure 48: Terminated HSTL Class IV
Figure 47: Terminated HSTL Class III
HSTL Class IV
V
(mA)
HSTL Class III
CCO
V
(mA)
CCO
= 1.5V
= 1.5V
Figure
V
V
REF
CCO
V
50Ω
TT
1.40
Min
−8
48
V
V
= 1.5V
-
-
-
-
REF
Production Product Specification
+ 0.1
REF
– 0.4
48.
DS022-2 (v2.8) January 16, 2006
= 0.9V
= 0.9V
Z = 50
Z = 50
50Ω
V
50Ω
V
TT
TT
= 1.5V
= 1.5V
V
1.50
0.90
Typ
CCO
x133_11_111699
-
-
-
-
-
-
REF
x133_12_111699
is to be selected
V
REF
Max
1.60
0.4
-
-
-
-
-
-
– 0.1
R

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