MAX2163ETI/V+T Maxim Integrated Products, MAX2163ETI/V+T Datasheet - Page 17

• Manufacturer Part Number: MAX2163ETI/V+T
• Description: RF Receiver Low power TV tuner f or 1 segment ISDB-T
• Manufacturer: Maxim Integrated Products

Specifications of MAX2163ETI/V+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX2163 STBY can be controlled by either a hard-
ware pin or a register bit. The truth table for each is
described in Table 15.
For software control of the STBY mode, connect the
STBY pin to ground.
Table 16 defines the register setup for normal and high-
linearity modes.
The MAX2163 features a 2-wire I
interface consisting of a serial-data line (SDA) and a
serial-clock line (SCL). SDA and SCL facilitate bidirec-
tional communication between the MAX2163 and the
master at clock frequencies up to 400kHz. The master
device initiates a data transfer on the bus and generates
the SCL signal to permit data transfer. The MAX2163
functions as an I
receives data to and from the master. Pull SDA and SCL
high with external pullup resistors of 1kΩ or greater refer-
enced to MAX2163 V
One bit transfers during each SCL clock cycle. A mini-
mum of nine clock cycles is required to transfer a byte
into or out of the MAX2163 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START and STOP Conditions section). Both
SDA and SCL remain high when the bus is not busy.
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Normal and High-Linearity Mode
2
______________________________________________________________________________________
START and STOP Conditions
C slave device that transfers and
CCDIG
Pin and Bit Truth Tables
2-Wire Serial Interface
for proper I
2
C-compatible serial
2
C operation.
Definitions
ISDB-T 1-Segment Tuner
Table 15. Standby Bit Truth Table
Table 16. Register Setup for Normal and
High-Linearity Modes
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2163 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
STBY PIN
RFVGA
GND
GND
VCC
VCC
MIX
BIT
STBY BIT
NORMAL
MODE
0
0
0
1
0
1
Not-Acknowledge Conditions
Device in standby mode
Device in standby mode
Device in normal mode
Device in standby mode
HIGH LINEARITY MODE
DEVICE STATE
Acknowledge and
1
1
17