MAX2163ETI/V+T Maxim Integrated Products, MAX2163ETI/V+T Datasheet - Page 21

• Manufacturer Part Number: MAX2163ETI/V+T
• Description: RF Receiver Low power TV tuner f or 1 segment ISDB-T
• Manufacturer: Maxim Integrated Products

Specifications of MAX2163ETI/V+T

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX2163 includes a 3-bit ADC. Its input is con-
nected to the VCO tune pin (VTUNE). This ADC can be
used for checking the lock status of the VCOs.
Table 19 summarizes the phase-locked loop (PLL) lock
status based on ADC[2:0] values. The VCO autoselect
routine only selects a VCO in the VAS locked range.
This allows room for a VCO to drift over temperature
and remain in a valid locked range.
When VCO autoselect is disabled, the ADC must first be
enabled by setting the ADE bit in the VAS register. The
ADC reading is latched by a subsequent programming
of the ADC latch bit (ADL = 1). The ADC value is reported
in the STATUS register (Table 12).
The loop-time constant (LTC) function sets the wait time
for an ADC read when in VCO autoselect mode. This
wait time determines how long the VCO autoselect cir-
cuit waits for the PLL to settle before determining if
VCO selection was successful. The loop time constant
is selectable by the LTC[1:0] bits in the VAS register
(Table 4).
The reference buffer/divider is provided for driving
external devices. The internal frequency divider is fixed
at 2, and the buffer can provide a minimum 500mV
signal swing into a load of 4kΩ||10pF with a guaranteed
duty cycle of 45% to 55%. Upon power-up or coming
out of shutdown, the XTALOUT buffer is held in shut-
down for an additional 3ms (typ) by an internal timer
circuit. This allows the crystal oscillator sufficient time to
start up properly, without unwanted parasitic feedback
from the output buffer.
Table 19. PLL and Lock Status
ADC[2:0]
000
001
010
011
100
101
110
111
3-Bit Analog-to-Digital Converter
Loop-Time Constant Selection
______________________________________________________________________________________
PLL LOCK STATUS
XTALOUT Buffer
Out of lock
Unlocked
Not used
Not used
Locked
Locked
Locked
Locked
P-P
ISDB-T 1-Segment Tuner
The MAX2163 Evaluation Kit serves as a guide for PCB
layout. Keep RF signal lines as short as possible to mini-
mize losses and radiation. Use controlled impedance on
all high-frequency traces. Use abundant ground vias
between RF traces to minimize undesired coupling.
Bypass each V
placed as close as possible to the pin.
When using the optional UHF tracking filter, keep the
external inductor as close to the IC as possible and allow
it to connect back to the top side ground as close as
possible to the IC.
To ensure proper crystal oscillator startup, place the
crystal near the MAX2163 XTAL pin (pin 21). The crys-
tal ground should have a clear, short return back to the
MAX2163 ground paddle near XTAL. Minimize the par-
asitic capacitance between the board traces of XTAL
(pin 21) and XTALOUT (pin 22). Refer to the MAX2163
Evaluation Kit data sheet for a recommended board
layout.
In addition, the ground returns for the VCO, VTUNE,
and charge pump require special layout consideration
(see the Typical Application Circuit ). The LDO capaci-
tor (C66) and VCCVCO bypass capacitor (C17)
grounds should be routed back to the MAX2163
ground paddle near pin 28. The loop filter ground con-
nections of C27, C28, and C30 should be connected
together before tapping down to the overall ground
plane with a clear path back to pin 25 (GNDSYN).
When using the TQFN packaged device, the exposed
paddle must be soldered evenly to the board’s ground
plane for proper operation. Use abundant vias beneath
the exposed paddle for maximum heat dissipation.
CC_
pin to ground with a 0.1µF capacitor
Layout Considerations
21