71M6541F-DB Maxim Integrated Products, 71M6541F-DB Datasheet - Page 107
71M6541F-DB
Manufacturer Part Number
71M6541F-DB
Description
Power Management Modules & Development Tools 71M6541 Eval Kit
Manufacturer
Maxim Integrated Products
Datasheet
1.71M6541F-DB.pdf
(165 pages)
Specifications of 71M6541F-DB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 75
have a darker gray background.
v1.1
CE and ADC
CLOCK GENERATION
LCD/DIO
VREF TRIM FUSES
LCD_MAP6
LCD_MAP5
LCD/DIO
TRIMT
CKGN
Name
MUX5
MUX4
MUX3
MUX2
MUX1
MUX0
RTM0
RTM0
RTM1
RTM2
RTM3
LCD0
LCD1
LCD2
CE6
CE5
CE4
CE3
CE2
CE1
CE0
lists bits and registers that may have to be accessed on a frequent basis. Reserved bits have lighter gray background, and non-volatile bits
Addr
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
210A
210B
210C
210D
210E
210F
2110
2111
2200
2309
2400
2401
2402
2405
2406
LCD_BAT
LCD_E
Bit 7
LCD_VMODE[1:0]
U
U
U
U
R
EQU[2:0]
Bit 6
U
U
R
U
U
R
MUX9_SEL[3:0]
MUX7_SEL[3:0]
MUX5_SEL[3:0]
MUX3_SEL[3:0]
MUX1_SEL[3:0]
MUX_DIV[3:0]
© 2008–2011 Teridian Semiconductor Corporation
Table 75: I/O RAM Map – Functional Order
LCD_MODE[2:0]
ADC_DIV
DIFFB_E
Bit 5
U
U
PLL_FAST
DIFFA_E
PLS_MAXWIDTH[7:0]
Bit 4
PLS_INTERVAL[7:0]
U
SUM_SAMPS[7:0]
U
LCD_MAP[55:48]
LCD_MAP[47:40]
TRIMT[7:0]
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
LCD_ALLCOM
RFLY_DIS
LCD_BLNKMAP23[5:0]
LCD_BLNKMAP22[5:0]
RESET
Bit 3
U
CE_LCTN[5:0]
CHOP_E[1:0]
SUM_SAMPS[12:8]
LCD_Y
Bit 2
MUX10_SEL[3:0]
U
MUX8_SEL[3:0]
MUX6_SEL[3:0]
MUX4_SEL[3:0]
MUX2_SEL[3:0]
MUX0_SEL[3:0]
FIR_LEN[1:0]
MPU_DIV[2:0]
RTM_E
Bit 1
LCD_CLK[1:0]
RTM0[9:8]
PLS_INV
CE_E
Bit 0
107
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