71M6541F-DB Maxim Integrated Products, 71M6541F-DB Datasheet - Page 50

• Manufacturer Part Number: 71M6541F-DB
• Description: Power Management Modules & Development Tools 71M6541 Eval Kit
• Manufacturer: Maxim Integrated Products

Specifications of 71M6541F-DB

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock (RTC)
When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the PLL
2.5.1.2 MPU/CE RAM
The 71M6541D includes 3 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal RAM in
the MPU core. The 71M6541D/F and the 71M6542F include 5 KB of static RAM memory on-chip (XRAM)
plus 256 bytes of internal RAM in the MPU core. The static RAM is used for data storage for both MPU
and CE operations.
2.5.1.3 I/O RAM (Configuration RAM)
The I/O RAM can be seen as a series of hardware registers that control basic hardware functions. I/O
RAM address space starts at 0x2000. The registers of the I/O RAM are listed in
The 71M6541D/F and 71M6542F include 128 bytes non-volatile RAM memory on-chip in the I/O RAM
address space (addresses 0x2800 to 0x287F). This memory section is supported by the voltage applied
at VBAT_RTC and the data in it are preserved in BRN, LCD, and SLP modes as long as the voltage at
VBAT_RTC is within specification.
2.5.2 Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. This type of crystal is accurate and does not
require a high-current oscillator circuit. The oscillator has been designed specifically to handle watch
crystals and is compatible with their high impedance and limited power handling capability. The oscillator
power dissipation is very low to maximize the lifetime of any battery attached to VBAT_RTC.
Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to
The oscillator is powered from the V3P3SYS pin or from the VBAT_RTC pin, depending on the V3OK
internal bit (i.e., V3OK = 1 if V3P3SYS ≥ 2.8 VDC and V3OK = 0 if V3P3SYS < 2.8 VDC). The oscillator
requires approximately 100 nA, which is negligible compared to the internal leakage of a battery.
2.5.3 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to produce 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is
derived from MCK.
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see
Timers and
The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by
another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be
set to MCK*2
current is reduced by reducing the MPU clock frequency. When the ICE_E pin is high, the circuit also
generates the 9.83 MHz clock for use by the emulator.
The PLL is only turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
value depends on the setting of the LCD_VMODE [1:0] field (see Table 56).
frequency is not be accurate until the PLL_OK flag (SFR 0xF9[4]) rises. Due to potential overshoot, the MPU
should not change the value of PLL_FAST until PLL_OK is true.
50
Counters).
for more information.
-(MPU_DIV+2)
Table 41
, where MPU_DIV[2:0] may vary from 0 to 4. The 71M654x V3P3SYS supply
© 2008–2011 Teridian Semiconductor Corporation
provides a summary of the clock functions and their controls.
Table
74.
2.5.4, Real-Time
2.4.6
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