XC6SLX45T-3FGG484C Xilinx Inc, XC6SLX45T-3FGG484C Datasheet - Page 55

• Manufacturer Part Number: XC6SLX45T-3FGG484C
• Description: FPGA Spartan®-6 Family 43661 Cells 45nm (CMOS) Technology 1.2V 484-Pin FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan® 6 LXTr

Specifications of XC6SLX45T-3FGG484C

• Package: 484FBGA
• Family Name: Spartan®-6
• Device Logic Cells: 43661
• Device Logic Units: 27288
• Number Of Registers: 54576
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 296
• Ram Bits: 2138112
• Package / Case: 484-BGA
• Mounting Type: Surface Mount
• Voltage - Supply: 1 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Number Of I /o: 296
• Number Of Logic Elements/cells: 43661
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 55: Switching Characteristics for the Digital Frequency Synthesizer DFS (DCM_CLKGEN)
Table 56: Recommended Operating Conditions for the Phase-Shift Clock in Variable Phase Mode (DCM_SP) or
Dynamic Frequency Synthesis (DCM_CLKGEN)
DS162 (v2.0) March 31, 2011
Preliminary Product Specification
Notes:
1.
2.
3.
4.
5.
6.
Spread Spectrum
F
SPECTRUM
T
T
F
SPECTRUM
Operating Frequency Ranges
PSCLK_FREQ
Input Pulse Requirements
PSCLK_PULSE
CLKIN_FIXED_SPREAD_
CENTER_LOW_SPREAD
CENTER_HIGH_SPREAD
MOD_FIXED_SPREAD_
The values in this table are based on the operating conditions described in
For optimal jitter tolerance and a faster LOCK time, use the CLKIN_PERIOD attribute.
Output jitter is characterized with no input jitter. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply, and PCB design. The actual maximum output jitter depends on
the system application.
The CLKFX, CLKFXDV, and CLKFX180 outputs have a duty cycle of approximately 50%.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, this data sheet specifies a maximum
CLKFX jitter of ±(1% of CLKFX period + 200 ps). Assuming that the CLKFX output frequency is 100 MHz, the equivalent CLKFX period is 10 ns, and
1% of 10 ns is 0.1 ns or 100 ps. Accordingly, the maximum jitter is ±(100 ps + 200 ps) = ±300 ps.
When using CENTER_LOW_SPREAD, CENTER_HIGH_SPREAD, the valid values for CLKFX_MULTIPLY are limited to 2 through 32, and the valid
values for CLKFX_DIVIDE are limited to 1 through 4.
Symbol
Symbol
(6)
(6)
(6)
Frequency for the PSCLK input.
PSCLK pulse width as a
percentage of the PSCLK period.
Frequency of the CLKIN input for
fixed spread spectrum
(SPREAD_SPECTRUM =
CENTER_LOW_SPREAD/
CENTER_HIGH_SPREAD)
Spread at the CLKFX output for
fixed spread spectrum
(SPREAD_SPECTRUM =
CENTER_LOW_SPREAD)
Spread at the CLKFX output for
fixed spread spectrum
(SPREAD_SPECTRUM=
CENTER_HIGH_SPREAD)
Average modulation frequency
when using fixed spread
spectrum
(SPREAD_SPECTRUM =
CENTER_LOW_SPREAD /
CENTER_HIGH_SPREAD)
Description
Description
www.xilinx.com
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
Min
30
Min
40
1
-3
Table 2
-3
Max
200
Max
167
60
and
Min
Table
Min
30
40
1
Typical
Typical
-3N
-3N
Typical = F
53.
Maximum = 250
Maximum = 400
Speed Grade
Speed Grade
Max
Max
200
167
60
=
=
----------------------------------------- -
CLKFX_DIVIDE
----------------------------------------- -
CLKFX_DIVIDE
IN
Min
Min
30
100
240
40
/1024
1
-2
-2
Max
Max
167
200
60
(1)
Min
Min
40
30
1
(Cont’d)
-1L
-1L
Max
100
Max
200
60
Units
Units
MHz
MHz
MHz
ps
ps
%
55