M5275EVBE Freescale, M5275EVBE Datasheet - Page 40

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M5275EVBE

Manufacturer Part Number
M5275EVBE
Description
Manufacturer
Freescale
Datasheet

Specifications of M5275EVBE

Lead Free Status / RoHS Status
Compliant
Electrical Characteristics
8.15
40
1
Num
J10
J11
J12
J13
J14
JTAG_EN is expected to be a static signal. Hence, it is not associated with any timing.
J1
J2
J3
J4
J5
J6
J7
J8
J9
QSPI_CS[3:0]
QSPI_DOUT
QSPI_CLK
QSPI_DIN
TCLK Frequency of Operation
TCLK Cycle Period
TCLK Clock Pulse Width
TCLK Rise and Fall Times
Boundary Scan Input Data Setup Time to TCLK Rise
Boundary Scan Input Data Hold Time after TCLK Rise
TCLK Low to Boundary Scan Output Data Valid
TCLK Low to Boundary Scan Output High Z
TMS, TDI Input Data Setup Time to TCLK Rise
TMS, TDI Input Data Hold Time after TCLK Rise
TCLK Low to TDO Data Valid
TCLK Low to TDO High Z
TRST Assert Time
TRST Setup Time (Negation) to TCLK High
JTAG and Boundary Scan Timing
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 4
QS3
Characteristics
QS1
Table 27. JTAG and Boundary Scan Timing
QS2
Figure 22. QSPI Timing
1
Symbol
t
t
t
t
t
t
t
t
TAPBST
TAPBHT
TRSTST
TRSTAT
TDODZ
f
t
BSDST
BSDHT
t
t
TDODV
t
t
JCYC
JCYC
BSDV
BSDZ
JCRF
JCW
QS4
4 x t
Min
100
DC
26
26
10
10
0
4
0
0
4
0
0
CYC
QS5
Freescale Semiconductor
Max
1/4
33
33
26
3
8
f
Unit
sys/2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns