MMCCMB2107 Freescale, MMCCMB2107 Datasheet - Page 590

• Manufacturer Part Number: MMCCMB2107
• Manufacturer: Freescale

Specifications of MMCCMB2107

• Lead Free Status / RoHS Status: Not Compliant

Electrical Specifications
22.8 PLL Electrical Specifications
Technical Data
590
PLL reference frequency range
System frequency
Loss of reference frequency
Self-clocked mode frequency
EXTAL input high voltage
EXTAL input low voltage
PLL lock time
Powerup-to-lock Time
1:1 clock skew (between CLKOUT and EXTAL)
Duty cycle of reference
Frequency un-LOCK range
Frequency LOCK range
CLKOUT period jitter
1. All internal registers retain data at 0 Hz.
2. Loss of reference frequency is the reference frequency detected internally, which transitions the PLL into self-clocked
3. Self-clocked mode frequency is the frequency that the PLL operates at when the reference frequency falls below f
4. This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the
5. Assuming a reference is available at power-up, lock time is measured from the time V
6. PLL is operating in 1:1 PLL mode.
7. Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
Crystal reference
External reference
1:1 mode
External reference
On-chip PLL frequency
Crystal mode
All other modes (1:1, bypass, external)
Crystal mode
All other modes (1:1, bypass, external)
Without crystal reference
Measured at f
Peak-to-peak jitter (clock edge to clock edge)
Long-term jitter (averaged over 2-ms interval)
mode.
default MFD/RFD settings.
synthesizer control register (SYNCR).
negating. If the crystal oscillator is being used as the reference for the PLL, then the crystal startup time must be added to
the PLL lock time to determine the total startup time.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the PLL circuitry via V
percentage for a given interval.
(4), (5)
(V
sys
DD
(1)
maximum
(7)
and V
(4), (5)
Parameter
(4)
(2)
DDSYN
(3)
Table 22-5. PLL Electrical Specifications
Freescale Semiconductor, Inc.
For More Information On This Product,
DDSYN
= 2.7 to 3.6 V, V
and V
Go to: www.freescale.com
Electrical Specifications
SSSYN
(6)
and variation in crystal oscillator frequency increase the C
SS
= V
Symbol
V
V
C
t
t
f
t
f
f
IHEXT
LPLK
Skew
ILEXT
LPLL
f
SCM
LOR
f
f
LCK
t
Jitter
sys
SSSYN
UL
ref
dc
= 0 V, T
V
DDSYN
V
V
f
–0.75
ref
SSSYN
SSSYN
–1.5
Min
100
0.5
2.0
DD
10
–2
40
—
—
—
—
2
2
0
/64
A
and V
–1.0
= T
DDSYN
L
to T
MMC2107 – Rev. 2.0
V
V
DDSYN
DDSYN
are valid to RSTOUT
Max
10.0
33.0
33.0
33.0
33.0
0.75
0.01
250
200
200
1.0
0.8
1.5
15
60
H
2
5
)
MOTOROLA
Jitter
sys
% f
% f
% f
% f
LOR
MHz
MHz
MHz
Unit
kHz
ns
V
V
.
s
s
sys
sys
sys
sys
with