SCANSTAEVK/NOPB National Semiconductor, SCANSTAEVK/NOPB Datasheet
SCANSTAEVK/NOPB
Specifications of SCANSTAEVK/NOPB
SCANSTAEVK/NOPB Summary of contents
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... The 7 slot inputs support up to 121 unique addresses, an Interrogation Address, Broadcast Address, and 4 Multi-cast Group Addresses (address 000000 is reserved) Connection Diagrams © 2005 National Semiconductor Corporation n 3 IEEE 1149.1-compatible configurable local scan ports n Mode Register selected for insertion into the scan chain individually, or serially in groups of two or three ...
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LFSR Linear Feedback Shift Register. When enabled, will generate a 16-bit signature of sampled serial test data. LSP Local Scan Port. A four signal port that drives a local (i.e. non-backplane) scan chain. (e.g., TCK TDO , TDI ). 0 ...
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Architecture Figure 1 shows the basic architecture of the ’STA111. The device’s major functional blocks are illustrated here. The TAP Controller, a 16-state state machine, is the central con- trol for the device. The instruction register and various test data ...
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No. Pin Name Pins I/O VCC 3 N/A Power GND 3 N/A Ground TMS 1 I BACKPLANE TEST MODE SELECT: Controls sequencing through the TAP Controller of the B ’STA111. Also controls sequencing of the TAPs which are on the ...
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No. Pin Name Pins I/O TRST 3 O LOCAL TEST RESETS: A gated version of TRST (0-2) current LOCAL PASS-THROUGH INPUTS: General purpose inputs which can be driven to the (0-1) backplane pin Y These inputs have ...
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State Machines (Continued) www.national.com FIGURE 2. SCANSTA111 State Machines 6 10124505 ...
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State Machines (Continued) The ’STA111 contains three distinct but coupled state- machines (see Figure 2). The first of these is the TAP-control state-machine, which is used to drive the ’STA111s scan ports in conformance with the 1149.1 Standard. The second ...
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State Machines (Continued) state) until the ’STA111 receives an UNPARK instruction and the ’STA111’s TAP state-machine enters the Run-Test/Idle state. Similarly, certain transitions of the scan port-configuration state-machine can force the ’STA111’s LSP-control state- machine into specific states. For example, ...
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State Machines (Continued) Following a hardware reset, the TAP controller state- machine is in the Test-Logic-Reset (TLR) state; the ’STA111- selection state-machine is in the Wait-For-Address state; and each of the three port-selection state-machines is in the Parked-TLR state. The ...
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Level 1 Protocol (Addressing Modes) Address Type Hex Address Direct Address 7F. ( (Note 4)) Interrogation Address 3A Broadcast Address 3B Multi-Cast Group 0 3C Multi-Cast Group 1 3D Multi-Cast Group 2 3E ...
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Level 1 Protocol (Addressing Modes) FIGURE 7. Broadcast Addressing: Address Loaded into Instruction Register FIGURE 8. Multi-Cast Addressing: Address Loaded into Instruction Register Level 2 Protocol Once the SCANSTA111 has been successfully addressed and selected, its internal registers may be ...
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Level 2 Protocol (Continued) Pause-IR and the active scan chain consists of: TDI through the instruction register (or the IDCODE register) and out through TDO . B → Instruction Register → TDO TDI B The UNPARK instruction (described later) is ...
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Level 2 Protocol (Continued) Instructions Hex Op-Code BYPASS EXTEST SAMPLE/PRELOAD IDCODE UNPARK PARKTLR PARKRTI PARKPAUSE GOTOWAIT (Note 5) MODESEL MODESEL 1 MODESEL 2 MODESEL 3 MCGRSEL SOFTRESET LFSRSEL LFSRON LFSROFF CNTRSEL CNTRON CNTROFF DEFAULT_BYPASS (Note 6) TRANSPARENT0 TRANSPARENT1 TRANSPARENT2 TRANSPARENT3 ...
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Level 2 Protocol (Continued) TABLE 5. Level 2 Protocol and Op-Codes (Continued) Instructions Hex Op-Code DGPIO 4 DGPIO 5 DGPIO 6 DGPIO 7 SGPIO 0 SGPIO 1 SGPIO 2 SGPIO 3 SGPIO 4 SGPIO 5 SGPIO 6 SGPIO 7 Other ...
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Level 2 Protocol (Continued) ’STA111s connected to the backplane. The PARKPAUSE instruction is scanned into the selected ’STA111s and the ’STA111 TAP controllers are sequenced to the Pause-DR state where the LSPs of all ’STA111s become unparked. The local TAP ...
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Level 2 Protocol (Continued) FIGURE 10. Local Scan Port Synchronization from Parked-RTI State Register Descriptions INSTRUCTION REGISTER: The instruction shift register is an 8-bit register that is in series with the scan chain when- ever the TAP Controller of the ...
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Register Descriptions TABLE 7. Mode Register Control of LSPN (Continued) Mode Register(s) Scan Chain Configuration (if unparked) → Register → LSP MR0: X000X001 TDI B → Register → LSP MR0: X000X010 TDI B → Register → LSP MR0: X000X011 TDI ...
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Register Descriptions count (zero cleared (logic 0) when the counter is loaded following a CNTRSEL instruction. The power-on value for bit BIT 7 Description TCK Counter Status LSP Used in Silicon Y Default Value 0 ...
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Special Features TRANSPARENT MODE While this mode is activated, the selected LSP n ports will follow the backplane ports. TRST is a buffered version of n TRST , TCK is a buffered version of TCK B n buffered version of ...
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Special Features (Continued) FIGURE 11. Local Scan Port Synchronization on Second Pass FIGURE 12. Synchronization of the Three Local Scan Ports This moves the local chain TAP Controllers to the synchro- nization state (Run-Test/Idle), where they stay until synchro- nization ...
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Special Features (Continued) • Number/Type of GPIO bits: The STA111 has both dedi- cated and shared GPIO (General Purpose I/O). Each dedicated group of GPIO bits supports from dedi- cated inputs and dedicated outputs. ...
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Special Features (Continued) registers (one register per LSP). The GPIO outouts are updated during the UPDATE-DR state and the GPIO input values are written to the corresponding GPIO register during the CAPTURE-DR state. LSP SHARED: In the shared mode of ...
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Special Features (Continued) FIGURE 13. Address Interrogation State Machine 23 10124504 www.national.com ...
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Absolute Maximum Ratings Supply Voltage ( Input Diode Current ( −0. Input Voltage ( Output Diode Current ( −0. Output Voltage (V ...
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DC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified Symbol Parameter V Maximum Low Output Voltage OL (TRIST , TRIST , LSP_ACTIVE B (0-2) I Maximum Input Leakage Current IN (TCK , ...
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AC Electrical Characteristics Over recommended operating supply voltage and temperature ranges unless otherwise specified. Symbol Parameter t , Propagation Delay PHL15 t TMS to TMS PLH15 B (0- Propagation Delay PHL16 t TDI to TDO PLH16 B (0-2) ...
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AC Loading and Waveforms FIGURE 14. AC Test Circuit (C FIGURE 15. Waveforms for an Unparked STA111 in the Shift-DR (IR) TAP Controller State includes probe and jig capacitance 6.0V 50pF AC Waveforms 27 10124520 ...
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AC Loading and Waveforms www.national.com (Continued) FIGURE 16. Reset Waveforms FIGURE 17. Output Enable Waveforms 28 10124538 10124539 ...
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AC Loading and Waveforms Waveform for Inverting and Non-inverting Functions Propagation Delay, Pulse Width and t (Input Characteristics 1MHz, t Capacitance & I/O Characteristics Refer to National’s website for IBIS models at http://www.national.com/scan (Continued) 10124521 Tristate Output High ...
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Physical Dimensions unless otherwise noted www.national.com inches (millimeters) 48-Pin TSSOP NS Package Number MTD48 Ordering Code SCANSTA111MT 49-Pin BGA NS Package Number SLC49a Ordering Code SCANSTA111SM 30 ...
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... BANNED SUBSTANCE COMPLIANCE National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2. ...