SCANSTAEVK/NOPB National Semiconductor, SCANSTAEVK/NOPB Datasheet - Page 9

• Manufacturer Part Number: SCANSTAEVK/NOPB
• Manufacturer: National Semiconductor

Specifications of SCANSTAEVK/NOPB

• Lead Free Status / RoHS Status: Compliant

Register Name
Instruction Register
Boundary-Scan Register
Bypass Register
Device Identification Register
Multi-Cast Group Register
Mode Register
Mode Register
Mode Register
Linear-Feedback Shift
Register
TCK Counter Register
Dedicated GPIO Register
Shared GPIO Register
State Machines
Following a hardware reset, the TAP controller state-
machine is in the Test-Logic-Reset (TLR) state; the ’STA111-
selection state-machine is in the Wait-For-Address state;
and each of the three port-selection state-machines is in the
Parked-TLR state. The ’STA111 is then ready to receive
Level-1 protocol, followed by Level-2 protocol.
Tester/SCANSTA111 Interface
An IEEE 1149.1 system tester sends instructions to a
’STA111 via that ’STA111’s backplane scan-port. Following
test logic reset, the ’STA111’s selection state-machine is in
the Wait-For-Address state. When the ’STA111’s TAP con-
troller is sequenced to the Shift-IR state, data shifted in
through the TDI
tion register. Note that prior to successful selection of a
’STA111, data is not shifted out of the instruction register and
out through the ’STA111’s TDO
mal scan operations. Instead, as each new bit enters the
instruction register’s most-significant bit, data shifted out
from the least-significant bit is discarded.
When the instruction register is updated with the address
data, the ’STA111’s address-recognition logic compares the
seven least-significant bits of the instruction register with the
7-bit assigned address which is statically present on the
S
compared with the reserved Broadcast and Multi-cast ad-
dresses. If an address match is detected, the ’STA111-
selection state-machine enters one of the two selected
states. If the scanned address does not match a valid single-
slot address or one of the reserved broadcast/multi-cast
addresses, the ’STA111-selection state-machine enters the
Unselected state.
Note 2: One dedicated and one shared GPIO register exists for each LSP that supports dedicated and/or shared GPIO (maximum of eight shared and eight
dedicated GPIO registers).
Note 3: HDL version only
(0-6)
inputs. Simultaneously, the scanned-in address is
0
1
2
B
input is shifted into the ’STA111’s instruc-
(0-n)
(0-n)
(Continued)
B
BSDL Name
INSTRUCTION
BOUNDARY
BYPASS
IDCODE
MCGR
MODE
(TBD)
(TBD)
LFSR
CNTR
(TBD)
(TBD)
output, as it is during nor-
TABLE 3. Register Descriptions
Description
STA111 addressing and instruction-decode IEEE Std. 1149.1 required
register
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 required register
IEEE Std. 1149.1 optional register
STA111-group address assignment
STA111 local-port configuration and control bits
STA111 local-port configuration and control bits (Note 2)
STA111 Shared GPIO configuration bits
STA111 scan-data compaction (signature generation)
Local-port TCK clock-gating (for BIST)
STA111 Dedicated GPIO control bits (Note 3)
STA111 Shared GPIO control bits (Note 3)
9
Note that the SLOT inputs should not be set to a value
corresponding to a multi-cast group, or to the broadcast
address. Also note that the single ’STA111 selection process
must be performed for all ’STA111s which are subsequently
to be addressed in multi-cast mode. This is required be-
cause each such device’s Multicast Group Register (MCGR)
must be programmed with a multi-cast group number, and
the MCGR is not accessible to the test controller until that
’STA111 has first entered the Selected-Single-’STA111 state.
Once a ’STA111 has been selected, Level-2 protocol is used
to issue commands and to access the chip’s various regis-
ters.
Register Set
The SCANSTA111 includes a number of registers which are
used for ’STA111 selection and configuration, scan data
manipulation, and scan-support operations. These registers
can be grouped as shown in Table 3.
The specific fields and functions of each of these registers
are detailed in the section of this document titled Data Reg-
ister Descriptions.
Note that when any of these registers is selected for inser-
tion into the ’STA111’s scan-chain, scan data enters through
that register’s most-significant bit. Similarly, data that is
shifted out of the register is fed to the scan input of the
next-downstream device in the scan-chain.
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