DEMO9S08LIN Freescale, DEMO9S08LIN Datasheet - Page 134

• Manufacturer Part Number: DEMO9S08LIN
• Manufacturer: Freescale

Specifications of DEMO9S08LIN

• Lead Free Status / RoHS Status: Compliant

Chapter 9 Liquid Crystal Display Driver (S08LCDV1)
9.3.6
Read: anytime
Write: anytime. It is recommended that VSUPPLY[1:0] must not be modified while the LCDEN bit is
asserted. In addition, VSUPPLY[1:0] must be configured according to the external hardware power supply
configuration.
134
CLKADJ[5:0
LCDCPMS
LCDCPEN
SOURCE
Reset
DIV16
Field
Field
5:0
7
6
7
6
]
W
R
LCDCPEN
LCD Voltage Supply Register (LCDSUPPLY)
LCD Clock Source Select — The LCD module has two possible clock sources. This bit is used to select which
clock source is the basis for LCDCLK.
0 Selects the ICGERCLK (external clock reference) as the LCD clock source.
1 Selects the ICGOUT/2 (bus clock) as the LCD clock source.
LCD Clock Prescaler Enable— Enable prescaler by 16.
0 LCD clock prescaler is disabled.
1 LCD clock prescaler is enabled.
LCD Clock Source Divider— The LCD module is designed to operate using a 32.768 kHz clock source for
reduced power consumption (LCDCLK = 32.768 kHz). This bit field is used as a clock divider to adjust the LCD
clock source to be approximately 32.768 kHz.
0
7
LCD Module Charge Pump Enable— Enables LCD module charge pump for 1/3 bias.
0 LCD charge pump is disabled. (An external bias is required.)
1 LCD charge pump is enabled. (The internal 1/3-bias is forced.)
LCD Module Charge Pump Mode Select— This configuration depends on whether the LCD panel operating
voltage is specified as 3 V or 5 V. LCDCPMS configures the internal charge pump to be a voltage doubler
(recommended for use with 3-V LCD glass) or a voltage tripler (recommended for use with 5-V LCD glass).
0 Selects voltage doubler.
1 Selects voltage tripler.
Unimplemented or Reserved
LCDCPMS
Figure 9-7. LCD Voltage Supply Register (LCDSUPPLY)
0
6
LCDCLK =
MC9S08LC60 Series Data Sheet: Technical Data, Rev. 4
Table 9-10. LCDSUPPLY Field Descriptions
Table 9-9. LCDCLKS Field Descriptions
CPCADJ1
1
5
LCD clock source / (16
CPCADJ0
1
4
Description
Description
HDRVBUF
DIV16
3
0
×
(CLKADJ[5:0] +1)
BBYPASS
1
2
)
VSUPPLY1
Freescale Semiconductor
0
1
VSUPPLY0
Eqn. 9-2
1
0